Total ionization dose effects of N-type tunnel field effect transistor (TFET) with ultra-shallow pocket junction

Xi, Kai; Bi, Jinshun; Chu, Jiamin; Xu, Gaobo; Li, Bo; Wang, Haibin; Liu, Ming; Majumdar, Sandip

doi:10.1007/s00339-020-03622-2

Cited by 10 publications

(3 citation statements)

References 28 publications

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“…The radiation-induced soft errors have been assessed for Si FinFET, III–V (InAs) FinFET, and III–V (GaSb Source/InAs Channel-Drain) HTFET 33 . An excellent anti-radiation performance has been achieved using an N-type TFET with a Si 1−x Ge x /Si hetero-junction in the ultra-shallow N+ pocket region 34 . The Vertical JLFET with the Ge source region obtained an improved radiation hardness 35 .…”

Section: Introductionmentioning

confidence: 99%

TCAD simulation study of heavy ion radiation effects on hetero junctionless tunnel field effect transistor

Aishwarya,

Lakshmi

2024

Sci Rep

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Semiconductor devices used in radiation environment are more prone to degradation in device performance. Junctionless Tunnel Field Effect Transistor (JLTFET) is one of the most potential candidates which overcomes the short channel effects and fabrication difficulties. In this work, 20 nm JLTFET is proposed with Silicon in the drain/channel region whereas source uses different materials, Silicon Germanium (SiGe), Gallium Nitride (GaN), Gallium Arsenide (GaAs), Indium Arsenide (InAs). The device performance is examined by subjecting it to heavy ion radiation at a lower and higher dose of linear energy transfer (LET) values. It can be seen that the most sensitive location is the source/channel (S/C) interface for SiGe, GaN and GaAs whereas the drain/channel (D/C) interface for InAs. Further analysis is carried out at these vulnerable regions by matching ION of all materials. The parameters, transient peak current (Ipeak), collected charge (QC), threshold voltage shift (ΔVth) and bipolar gain (β) are extracted using transient simulations. It is observed that for a lower dose of LET, Ipeak of SiGe is 27% lesser than InAs and for higher dose of LET, SiGe shows 56% lesser Ipeak than InAs. SiGe is less sensitive at lower and higher dose of LET due to reduced ΔVth, tunneling and electron density.

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Section: Introductionmentioning

confidence: 99%

TCAD simulation study of heavy ion radiation effects on hetero junctionless tunnel field effect transistor

Aishwarya,

Lakshmi

2024

Sci Rep

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“…Recently, TID on the electrical characteristics of heterojunction NTFETs has been studied. Studies have shown that under the same TID conditions, P-well TFETs are more robust than P-well-less TFETs [ 21 ]. This laid the foundation for the future manufacture of the heterojunction TFET’s anti-irradiation reinforcement process.…”

Section: Introductionmentioning

confidence: 99%

Study on Single Event Effect Simulation in T-Shaped Gate Tunneling Field-Effect Transistors

et al. 2021

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Tunneling field-effect transistors (TFETS) can reduce the subthreshold swing (SS) to below 60 mV/decade due to their conduction mechanism with band-to-band tunneling (BTBT), thereby reducing power consumption. T-shaped gate tunneling field-effect transistors (TGTFET) adapt double source and T-shaped gates to enhance the on-state current and to generate the tunneling probability. In this paper, TGTFET subjected to heavy-ion irradiation is studied by technology computer-aided design (TCAD) simulation for the first time. The results show that as the drain bias and linear energy transfer (LET) increase, the transient current and collected charge also increase. When LET = 100 MeV·cm2/mg and Vd = 0.5 V, the transient current of TGTFET is as high as 10.63 mA, which is much larger than the on-state current. This means that TGTFET is more sensitive to single-event effect (SEE) than FDSOI. By simulating a heavy-ion strike on different locations in TGTFET, the tunneling junction is the most sensitive region of SEE. This provides guidance for future research on the antiradiation application of TFET-based devices.

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“…Tunnelling field-effect transistors (TFET), based on the band-to-band tunnelling (BTBT) mechanism, are expected to overcome these issues. Therefore, TFET is considered one of the potential candidates of nano-scale MOS-FET [3,4]. While TFET shows the advantages of smaller I OFF and steeper SS over traditional MOSFET, it still faces many challenges.…”

Section: Introductionmentioning

confidence: 99%

Numerical simulation of vertical tunnelling field-effect transistors charge-trapping memory with TCAD tools

Cao

Tian

Majumdar

et al. 2021

Semicond. Sci. Technol.

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A novel vertical tunnelling field-effect transistor (TFET) based on silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory device, named as VT-SONOS, is proposed and investigated using TCAD simulations. Different from traditional planar TFET-based SONOS memory, the VT-SONOS device is programmed via band-to-band tunnelling for vertical pocket and Fowler–Nordheim tunnelling for both pocket/bottom oxide (OXb) and channel/OXb regions, which leads to a steeper subthreshold swing (SS) and a larger on-state current (I ON). The device structure is constructed using Sentaurus TCAD tools, and I D–V G characteristics were extracted using TCAD tools. Obtained SS value is 102.09 mV dec−1, while the I ON was 3.02 × 10−4 A. The memory window was 2.95 V, showing more dependence on programming pulse height (V gp) than erasing pulse height (V ge). Furthermore, 10-year retention characteristics were studied to investigate critical reliability issue. About 60% of the initial trapped charges remained in the device after unbiased 3.15 × 108 s (10 years) storage.

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Total ionization dose effects of N-type tunnel field effect transistor (TFET) with ultra-shallow pocket junction

Cited by 10 publications

References 28 publications

TCAD simulation study of heavy ion radiation effects on hetero junctionless tunnel field effect transistor

TCAD simulation study of heavy ion radiation effects on hetero junctionless tunnel field effect transistor

Study on Single Event Effect Simulation in T-Shaped Gate Tunneling Field-Effect Transistors

Numerical simulation of vertical tunnelling field-effect transistors charge-trapping memory with TCAD tools

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