Total Dose and Single-Event Effects Testing of the Intersil ISL70321SEH Power Supply Sequencer

Vonno, N. W. van; Mansilla, O.; Turner, S. D.; Newman, W. H.; Pearce, L. G.; Thomson, E. J.

doi:10.1109/nsrec.2018.8584283

Cited by 1 publication

(3 citation statements)

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“…Typical hardening methods are to increase the fault tolerance of the circuit, introduce a larger RC constant by directly increasing the capacitance value or adding the decoupling resistance, 20 and improve the critical charge by adjusting the device size. [21][22][23][24] These methods will cause great losses in speed, power, and area, and the hardening performance is limited. In addition, special processes developed for single-event latch-up (SEL) and enhanced low dose rate sensitivity (ELDRS) effect have also been reported.…”

Section: Previous Hardening Techniquesmentioning

confidence: 99%

“…In addition, special processes developed for single-event latch-up (SEL) and enhanced low dose rate sensitivity (ELDRS) effect have also been reported. 21,22 Triple modular redundant (TMR) is a common hardening technique. [21][22][23][24] The IS9-139ASRH hardened quad comparator developed based on Intersil's RSG process 21,22 makes redundancy for every comparator and current reference, so that each redundant comparator within each channel has a different current reference bias, which brings higher operating voltage, power consumption, and a larger area.…”

Section: Previous Hardening Techniquesmentioning

confidence: 99%

“…21,22 Triple modular redundant (TMR) is a common hardening technique. [21][22][23][24] The IS9-139ASRH hardened quad comparator developed based on Intersil's RSG process 21,22 makes redundancy for every comparator and current reference, so that each redundant comparator within each channel has a different current reference bias, which brings higher operating voltage, power consumption, and a larger area. It also greatly increases the complexity of the chip, bringing challenges to the layout and package.…”

Section: Previous Hardening Techniquesmentioning

confidence: 99%

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A novel high‐precision single‐event transient hardened voltage comparator design

Xie

Liu

et al. 2023

Circuit Theory & Apps

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SummaryTo reduce the impact of the single‐event transient (SET) effect on the high‐precision comparator, based on the common high‐gain pre‐amplification stage structure of the comparator, a new radiation hardened by design (RHBD) method, namely, the sensitive node transient detection feedback latch (SNTDFL) technique, is proposed. The hardening technique avoids comparator erroneous output by detecting the sensitive nodes of the high‐gain pre‐amplification stage. The detection circuit receives the response generated by the high energy particle impacts and feeds the high level back to the sensitive nodes to latch the current comparator state. In this paper, a novel high‐precision SET hardened voltage comparator based on this technique is developed. Through detailed circuit principle and simulation analysis, the functional characteristics and the hardening performance of the high‐precision hardened comparator are verified. Compared with the unhardened and the TMR technique hardened comparator, the SNTDFL technique hardened comparator effectively avoids the erroneous output caused by the SET effect with less overhead and still has excellent functional characteristics.

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