Topology aware mapping of logic functions onto nanowire-based crossbar architectures

Rao, Wenjing; Orailoğlu, Alex; Karri, Ramesh

doi:10.1145/1146909.1147093

Cited by 26 publications

(18 citation statements)

References 12 publications

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“…In [16], an application independent method was proposed where a defect-free subset of a defective crossbar was extracted as the functioning resource. The work in [18] translated the problem to a graph isomorphism model. The work in [19] presented a yield model for logic mapping based on searching monomorphism in graphs.…”

Section: Previous Workmentioning

confidence: 99%

Joint defect- and variation-aware logic mapping of multi-outputs crossbar-based nanoarchitectures

Ghavami

2016

J Comput Electron

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Nanotechnology-based manufacturing, relying on self-assembly of nanotubes or nanowires, has shown promising potentials for future nanoscale circuit designs. However, high defect density and extreme process variations for crossbar-based nanoarchitectures are expected to be fundamental design challenges. Consequently, defect and variation issues must be considered in logic mapping on nanoscale crossbars. In this paper, we establish a mathematical model for the simultaneous variation and defect-aware logic mapping of multi-outputs crossbar arrays. We model this problem using a new sub-weighted-graph isomorphism problem and propose a greedy algorithm for the variation-and defectaware logic mapping. Based on Monte-Carlo simulation, we compare the proposed technique with other logic mapping techniques such as, variation-unaware and exhaustive search mapping in terms of accuracy as well as runtime. Results show that the effectiveness of our new mapping technique in variation and defect tolerance as well as run time improvement.

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Section: Previous Workmentioning

confidence: 99%

Joint defect- and variation-aware logic mapping of multi-outputs crossbar-based nanoarchitectures

Ghavami

2016

J Comput Electron

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“…Work in [12], [13] utilizes the stuck-open defects by considering them as constraints during the logic mapping process. Besides crosspoint defects, [14] also explored open and bridging line defects.…”

Section: Introductionmentioning

confidence: 99%

Defect-tolerant logic implementation onto nanocrossbars by exploiting mapping and morphing simultaneously

Su¹,

Rao²

2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Crossbar-based architectures are promising for the future nanoelectronic systems. However, due to the inherent unreliability, defect tolerance schemes are necessary to guarantee the successful implementations of any logic functions. Most of the existing approaches have been based on logic mapping, which exploits the freedom of choosing which variables/products (in a logic function) to map to which of the vertical/horizontal wires (in a crossbar). In this paper, we propose a new defect tolerance approach, namely logic morphing, by exploiting the various equivalent forms of a logic function. This approach explores a new dimension of freedom in achieving defect tolerance, and is compatible with the existing mapping-based approaches. We propose an integrated algorithmic framework, which employs both mapping and morphing simultaneously, and efficiently searches for a successful logic implementation in the combined solution space. Simulation results show that the proposed scheme boosts defect tolerance capability significantly with many-fold yield improvement, while having no extra runtime over the existing approach of performing mapping alone.

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“…The other category was defect-using schemes. Work in [13] [14] considered stuck-open crosspoint defects imposing constraints on logic mapping. Besides crosspoint defects, [15] explores open and bridging line defects.…”

Section: Introductionmentioning

confidence: 99%

“…A more comprehensive model was used in [16]. Heuristics were proposed in [13] to reduce the runtime and [14] focused on yield simulation. Admittedly, no efficient scheme exists for the defect-tolerant mapping problem because of its complexity (NP-complete) shown in [13].…”

Section: Introductionmentioning

confidence: 99%

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Defect-Tolerant Logic Mapping on Nanoscale Crossbar Architectures and Yield Analysis

Rao

2009

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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Crossbar architectures are promising in the emerging nanoelectronic environment. However, fabrication processes for nano-scale circuits introduce numerous defects. Logic mapping on these defective nanofabrics thus emerges as a fundamental challenge. We establish a mathematical model for the logic mapping problem, followed by a probabilistic analysis to gain yield information. Since the most challenging part of the problem is the exponential runtime in searching for a solution, we examine the practical perspective of yield where a runtime limit is imposed. Yield improvement can be achieved through one of two ways: adding hardware redundancy by increasing crossbar size or allowing longer runtime. It turns out that correlations in the mapping solution space play an essential role on the complexity of the problem. Therefore, developing effective mechanisms to improve yield requires insights and analysis on correlations in the solution space. The analysis provided in this paper reveals the following points. Even though yield can always be improved through increasing crossbar size, the improvement gained by increasing crossbar size has a theoretical upperbound when a runtime limit is imposed. Consequently, there exists an optimal size for a crossbar to improve yield effectively within a runtime limit. Last but not least, for large-sized logic functions, longer runtime can be invested to improve yield significantly.

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Topology aware mapping of logic functions onto nanowire-based crossbar architectures

Cited by 26 publications

References 12 publications

Joint defect- and variation-aware logic mapping of multi-outputs crossbar-based nanoarchitectures

Joint defect- and variation-aware logic mapping of multi-outputs crossbar-based nanoarchitectures

Defect-tolerant logic implementation onto nanocrossbars by exploiting mapping and morphing simultaneously

Defect-Tolerant Logic Mapping on Nanoscale Crossbar Architectures and Yield Analysis

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