Top-Down PLL Design Methodology Combining Block Diagram, Behavioral, and Transistor-Level Simulators

Nicolle, B.; Tatinian, William; Mayol, J.-J.; Oudinot, J.; Jacquemod, G.

doi:10.1109/rfic.2007.380927

Cited by 5 publications

(1 citation statement)

References 1 publication

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“…In order to validate the system specifications, we included the phase noise simulation results into a high level PLL model (Matlab/Simulink) [8]. This mathematical modeling of the PLL behavior allows us to predict the total phase noise at the output of the PLL.…”

Section:  mentioning

confidence: 99%

RTW VCO with Switched-Capacitor Tuning for Satellite Communication Applications

Abdeljelil¹,

Tatinian²,

Jacquemod³

et al. 2007

2007 Ph.D Research in Microelectronics and Electronics Conference

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This paper shows the feasibility of combining Rotary Traveling Wave (RTW) oscillator and frequency switch tuning compensation based on a capacitor network to achieve a temperature and process variations robustness of Voltage Controlled Oscillators (VCO). This concept has been proved by combining transistor level simulations for the active part and electromagnetic simulations for the transmission lines. Global system specification have also been checked with high level Phase Locked Loop (PLL) modeling.

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Section:  mentioning

confidence: 99%

RTW VCO with Switched-Capacitor Tuning for Satellite Communication Applications

Abdeljelil¹,

Tatinian²,

Jacquemod³

et al. 2007

2007 Ph.D Research in Microelectronics and Electronics Conference

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On the use of behavioral modeling within the RFIC design flow: Satellite receiver case study

Nicolle

Khouri

Ferrero

et al. 2009

Microelectronics Journal

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Limitations of PLL simulation: Hidden oscillations in MatLab and SPICE

Bianchi

Kuznetsov

Леонов

et al. 2015

2015 7th International Congress on Ultra Modern Telecommunications and Control Systems and Workshops (ICUMT)

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Abstract-Nonlinear analysis of the phase-locked loop (PLL) based circuits is a challenging task, thus in modern engineering literature simplified mathematical models and simulation are widely used for their study. In this work the limitations of numerical approach is discussed and it is shown that, e.g. hidden oscillations may not be found by simulation. Corresponding examples in SPICE and MatLab, which may lead to wrong conclusions concerning the operability of PLL-based circuits, are presented.

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Top-Down PLL Design Methodology Combining Block Diagram, Behavioral, and Transistor-Level Simulators

Cited by 5 publications

References 1 publication

RTW VCO with Switched-Capacitor Tuning for Satellite Communication Applications

RTW VCO with Switched-Capacitor Tuning for Satellite Communication Applications

On the use of behavioral modeling within the RFIC design flow: Satellite receiver case study

Limitations of PLL simulation: Hidden oscillations in MatLab and SPICE

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