TooT: an efficient and scalable power-gating method for NoC routers

Farrokhbakht, Hossein; Taram, Mohammadkazem; Khaleghi, Behnam; Hessabi, Shaahin

doi:10.1109/nocs.2016.7579326

Cited by 25 publications

(7 citation statements)

References 22 publications

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“…As such they brought a trade off between performance and low power. The authors in [42] proposed a scalable power gating method Turn on-on Turn (TooT) for routers. In NoCs some routers remain idle for a long time, so when they wake up they consume power.…”

Section: 32mentioning

confidence: 99%

A Review of Design Approaches for Enhancing the Performance of NoCs at Communication Centric Level

Manzoor

Mir

Hakim

2021

SCPE

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As the trend of technology shrinking continues a vast amount of processors are being incorporated in a limited space. Due to this almost half of the chip area in Multi-Processor Systems-on-Chips (MPSoCs) is under interconnections, which pose a big problem for communication. Network-on-Chips (NoCs) evolved as a significant scalable solution for removing wiring congestion and communication problem in MPSoCs. NoCs provide the advantage of customized architecture, increased scalability and bandwidth. NoC is a structured framework where communication is the prime concern. In this review paper we present an overview of research and design approaches in the communication centric areas of NoCs. Here we have tried to discuss and iterate most of the available work done for communication in 2D NoCs. This paper gives the insight of different attributes and performance parameters of NoCs. Further it gives a detailed description of how topology, flow control and routing mechanisms can affect the qualitative aspects (performance) of NoCs. It then explains how various attributes of routing can help in increasing the efficacy of NoCs. Subsequently a brief review of different simulators used for NoCs is given. All of this is provided based on the survey of academic, theoretical and experimental approaches presented in the past. Finally some suggestions for future work are also given.

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Section: 32mentioning

confidence: 99%

A Review of Design Approaches for Enhancing the Performance of NoCs at Communication Centric Level

Manzoor

Mir

Hakim

2021

SCPE

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“…15 Farrokhbakht et al have proposed an efficient and scalable method for power gating NoC routers that reduces the wake ups by leveraging the characteristics of deterministic routing algorithms and mesh topology. 18 Similarly, Matsutani et al have proposed a sleep controlbased look ahead routing that identifies the packet arrival two hops ahead and thereby reducing the wake-up delay and frequent short-term sleep of channels. 17 Samih et al have proposed Router Parking technique for CMPs that selectively power-gates the routers attached to the idle cores.…”

Section: Related Workmentioning

confidence: 99%

Energy Efficient Network-on-Chip Architectures for Many-Core Near-Threshold Computing System

Rajamanikkam¹,

Rajesh²,

Chakraborty³

et al. 2019

Journal of Low Power Electronics

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Near threshold computing has unraveled a promising design space for energy efficient computing. However, it is still plagued by sub-optimal system performance. Application characteristics and hardware non-idealities of conventional architectures (those optimized for nominal voltage) prevent us from fully leveraging the potential of NTC systems. Increasing the computational core count still forms the bedrock of a multitude of contemporary works that address the problem of performance degradation in NTC systems. However, these works do not categorically address the shortcomings of the conventional on-chip interconnect fabric in a many core environment. In this work, we quantitatively demonstrate the performance bottleneck created by a conventional NTC architecture in many-core NTC systems. To reclaim the performance lost due to a sub-optimal NoC in many-core NTC systems, we propose BoostNoC-a power efficient, multi-layered network-on-chip architecture. BoostNoC improves the system performance by nearly 2× over a conventional NTC system, while largely sustaining its energy benefits. Further, capitalizing on the application characteristics, we propose two BoostNoC derivative designs: (i) PG BoostNoC; and (ii) Drowsy BoostNoC; to improve the energy efficiency by 1.4× and 1.37×, respectively over conventional NTC system.

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“…However, concerning this proposal, the complexity associated to the bypass flow control and VC selection is moved to the NI, which may increase its complexity and power consumption. Similarly, in [44] authors propose TooT, which relies on the fact that most of the traffic Chapter 2. Background and Related Work 24 crosses routers making no turns.…”

Section: Power-gatingmentioning

confidence: 99%

“…However, the complexity associated to the bypass flow control and VC selection is moved to the NI, which may increase its complexity and power consumption. In [44] authors propose TooT, which relies on the fact that most of the traffic crosses routers making no turns. Based on this fact, TooT switches most parts of the router off, and keeps on only a very reduced version of the router and one latch per port, allowing to forward traffic that requires no turns.…”

Section: Related Workmentioning

confidence: 99%

“…For our analysis we show results for a system provided with no power-gating mechanism, results for a system implementing PAPM and, additionally we compare also with TooT [44], a recent power-gating proposal described in Section 9.3, which essentially switches routers off and bypasses ports when traffic with no turns is detected.…”

Section: Performance Evaluation 951 Simulation Testbedmentioning

confidence: 99%

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Head-of-Line Blocking Reduction in Power-Efficient Networks-on-Chip

López¹,

José²

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TooT: an efficient and scalable power-gating method for NoC routers

Cited by 25 publications

References 22 publications

A Review of Design Approaches for Enhancing the Performance of NoCs at Communication Centric Level

A Review of Design Approaches for Enhancing the Performance of NoCs at Communication Centric Level

Energy Efficient Network-on-Chip Architectures for Many-Core Near-Threshold Computing System

Head-of-Line Blocking Reduction in Power-Efficient Networks-on-Chip

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