Titan-R: A Reconfigurable Hardware Implementation of a High-Speed Compressor

This paper presents a detailed analysis of various approaches to hardware implemented compression algorithm dictionaries, including our optimized method. To obtain comprehensive and detailed results, we introduced a method for the fair comparison of programmable hardware architectures to show the benefits of our approach from the perspective of logic resources, frequency, and latency. We compared two generally used methods with our optimized method, which was found to be more suitable for maintaining the memory content via (in)valid bits in any mid-density memory structures, which are implemented in programmable hardware such as FPGAs (Field Programmable Gate Array). The benefits of our new method based on a "Distributed Memory" technique are shown on a particular example of compression dictionary but the method is also suitable for another use cases requiring a fast (re-)initialization of the used memory structures before each run of an algorithm with minimum time and logic resources consumption. The performance evaluation of the respective approaches has been made in Xilinx ISE and Xilinx Vivado toolkits for the Virtex-7 FPGA family. However the proposed approach is compatible with 99% of modern FPGAs.

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Design of a High-Throughput Match Search Unit for Lossless Compression Algorithms

Bartík

Beneš

Kubalik

2019

2019 IEEE 9th Annual Computing and Communication Workshop and Conference (CCWC)

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Titan-R: A Reconfigurable Hardware Implementation of a High-Speed Compressor

Cited by 6 publications

References 23 publications

Combining hardware and software codecs to enhance data channels in FPGA streaming systems

Combining hardware and software codecs to enhance data channels in FPGA streaming systems

An In-Sight Into How Compression Dictionary Architecture Can Affect the Overall Performance in FPGAs

Design of a High-Throughput Match Search Unit for Lossless Compression Algorithms

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