TIP: Time-Proportional Instruction Profiling

Gottschall, Björn; Eeckhout, Lieven; Jahre, Magnus

doi:10.1145/3466752.3480058

Cited by 5 publications

(10 citation statements)

References 64 publications

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“…To eliminate the bias, they propose insertion of nop instructions after each monitored event. Gottschall et al [53] proposed an Oracle profiler as a golden reference for time-proportional attribution of event sampling. They found that existing PES facilities such as PEBS, IBS, and SPE are not…”

Section: Related Workmentioning

confidence: 99%

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Precise Event Sampling on AMD Versus Intel: Quantitative and Qualitative Comparison

Sasongko¹,

Chabbi²,

Unat³

2023

IEEE Trans. Parallel Distrib. Syst.

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Precise event sampling is a profiling feature in commodity processors that can sample hardware events and accurately locate the instructions that trigger the events. This feature has been used in a large number of tools to detect application performance issues. Although precise event sampling is readily supported in modern multicore architectures, vendor supports exhibit great differences that affect their accuracy, stability, overhead, and functionality. This work presents the most comprehensive study to date on benchmarking the event sampling features of Intel PEBS and AMD IBS and performs in-depth analysis on key differences through series of microbenchmarks. Our qualitative and quantitative analysis shows that PEBS allows finer-grained and more accurate sampling of hardware events, while IBS offers richer set of information at each sample though it suffers from lower accuracy and stability. Moreover, OS signal delivery, which is a common method used by the profiling software, introduces significant time overhead to the original overhead incurred by the hardware mechanisms in both PEBS and IBS. We also found that both PEBS and IBS have bias in sampling events across multiple different locations in a code. Lastly, we demonstrate how our findings on microbenchmarks under different thread counts hold for a full-fledged profiling tool that runs on the state-of-the-art Intel and AMD machines. Overall our detailed comparisons serve as a great reference and provide invaluable information for hardware designers and profiling tool developers.

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Section: Related Workmentioning

confidence: 99%

“…Gottschall et al [53] Sampling bias PEBS, IBS, ARM SPE They proposed a golden reference for time-proportional attribution of event sampling as PEBS, IBS, and SPE are not time-proportional in sampling events/instructions.…”

Section: Publication Evaluated Aspect(s) Pes Facilities Contributionsmentioning

confidence: 99%

Precise Event Sampling on AMD Versus Intel: Quantitative and Qualitative Comparison

Sasongko¹,

Chabbi²,

Unat³

2023

IEEE Trans. Parallel Distrib. Syst.

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“…Previous approaches to profiling can be divided into two broad categories. Sampling-based profiling [6], [10]- [15] interrupts program execution to read architectural performance counters, such as the number of CPU cycles and the number of § These authors contributed equally to this paper. cache misses since the last interrupt.…”

Section: Introductionmentioning

confidence: 99%

“…This breaks execution up into a number of samples, each associated with the program counter at the point that the interrupt occurs. With periodic or random sampling, the number of samples an instruction has is assumed to be proportional to the time used to execute the instruction by the processor [10], [15] (i.e. more samples means more time is spent on that instruction).…”

Section: Introductionmentioning

confidence: 99%

OptiWISE: Combining Sampling and Instrumentation for Granular CPI Analysis

Guo,

Chadwick,

Erdős

et al. 2024

2024 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)

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Despite decades of improvement in compiler technology, it remains necessary to profile applications to improve performance. Existing profiling tools typically either sample hardware performance counters or instrument the program with extra instructions to analyze its execution. Both techniques are valuable with different strengths and weaknesses, but do not always correctly identify optimization opportunities.We present OPTIWISE, a profiling tool that runs the program twice, once with low-overhead sampling to accurately measure performance, and once with instrumentation to accurately capture control flow and execution counts. OPTIWISE then combines this information to give a highly detailed per-instruction CPI metric by computing the ratio of samples to execution counts, as well as aggregated information such as costs per loop, source-code line, or function.We evaluate OPTIWISE to show it has an overhead of 8.1× geomean, and 57× worst case on SPEC CPU2017 benchmarks. Using OPTIWISE, we present case studies of optimizing selected SPEC benchmarks on a modern x86 server processor. The perinstruction CPI metrics quickly reveal problems such as costly mispredicted branches and cache misses, which we use to manually optimize for effective performance improvements.

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“…This is because the IBS precise event sampling facility in AMD machines implements a different heuristic compared to the PEBS facility in Intel machines. IBS implements dispatch‐tagging heuristic, which is similar to the one implemented in ARM processors, while PEBS implements Next‐Committing Instruction (NCI) heuristic 19 . Therefore, this work makes it much easier to develop profiling tools that target other microarchitectures, such as ARM, that sample instructions/events using similar dispatch‐tagging heuristic.…”

Section: Introductionmentioning

confidence: 99%

Precise event sampling‐based data locality tools for AMD multicore architectures

Sasongko

Chabbi²,

Unat

2023

Concurrency and Computation

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SummaryWe propose ComDetective, an inter‐thread communication analyzer, and ReuseTracker, a reuse distance analyzer, that leverage the hardware features in AMD processors to support low‐overhead profiling. Both tools employ the instruction‐based sampling (IBS) facility and debug registers in AMD processors to detect inter‐thread communication and data reuse. Different from prior arts, ComDetective differentiates the communication into true and false sharing, and ReuseTracker measures reuse distance in private and shared caches by also considering cache line invalidation with low overhead. Both tools can attribute the communications and reuses to source code lines. To our knowledge these tools are two of the few profiling tools designed specifically for AMD x86 architectures using IBS. Our tools are timely and relevant considering the rise in numbers of AMD processor based data centers and HPC systems. We perform experiments to evaluate the accuracy and overheads of the proposed tools on an AMD machine with two‐socket EPYC 7352 processors. ComDetective exhibits high accuracy while introducing 5.14 runtime and 1.4 memory overheads. ReuseTracker also displays high accuracy, which is 95%, with 11.76 runtime and 1.46 memory overheads. These overheads are much lower than the overheads of existing simulators and code instrumentation‐based tools. Lastly, we demonstrate the usage of the tools by having ComDetective and ReuseTracker facilitate the code refactoring of two data mining benchmarks to improve their performance by up to 29%.

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TIP: Time-Proportional Instruction Profiling

Cited by 5 publications

References 64 publications

Precise Event Sampling on AMD Versus Intel: Quantitative and Qualitative Comparison

Precise Event Sampling on AMD Versus Intel: Quantitative and Qualitative Comparison

OptiWISE: Combining Sampling and Instrumentation for Granular CPI Analysis

Precise event sampling‐based data locality tools for AMD multicore architectures

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