Timing predictability of cache replacement policies

Reineke, Jan; Grund, Daniel; Berg, Christoph; Wilhelm, Reinhard

doi:10.1007/s11241-007-9032-3

Cited by 149 publications

(101 citation statements)

References 7 publications

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“…This means that known precise and efficient cache analyses [5] for LRU can be applied to Selfish-LRU during WCET analysis. LRU is generally considered to be the most predictable replacement policy in the non-preemptive scenario [6].…”

Section: Useful Properties Of Selfish-lrumentioning

confidence: 99%

“…Work along these lines includes classifications of existing microarchitectures in terms of their predictability [17], [20], studies of the predictability of caches [6], and proposals of new microarchitectural techniques, such as novel multithreaded architectures that eliminate interference between threads [21], [22], [23], [24], [25] and DRAM controllers that allow multiple tasks to share DRAM devices in a predictable and composable fashion [26], [27]. In the following, we review work specifically concerning the interplay between multitasking and the memory hierarchy.…”

Section: Related Workmentioning

confidence: 99%

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Selfish-LRU: Preemption-aware caching for predictability and performance

Reineke

Altmeyer

Grund

et al. 2014

2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)

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Abstract-We introduce Selfish-LRU, a variant of the LRU (least recently used) cache replacement policy that improves performance and predictability in preemptive scheduling scenarios.In multitasking systems with conventional caches, a single memory access by a preempting task can trigger a chain reaction leading to a large number of additional cache misses in the preempted task. Selfish-LRU prevents such chain reactions by first evicting cache blocks that do not belong to the currently active task. Simulations confirm that Selfish-LRU reduces the CRPD (cache-related preemption delay) as well as the overall number of cache misses. At the same time, it simplifies CRPD analysis and results in smaller CRPD bounds.

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Section: Useful Properties Of Selfish-lrumentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Selfish-LRU: Preemption-aware caching for predictability and performance

Reineke

Altmeyer

Grund

et al. 2014

2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)

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“…Reineke et al analyzed the predictability of different cache replacement policies [33]. It is shown that the LRU policy performs best with respect to predictability.…”

Section: Related Workmentioning

confidence: 99%

“…The resulting FIFO strategy can be used for larger caches. To offset the less predictable behavior of the FIFO replacement [33], the cache has to be larger than an LRU based cache.…”

Section: Heap Allocated Objectsmentioning

confidence: 99%

Data cache organization for accurate timing analysis

2012

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Caches are essential to bridge the gap between the high latency main memory and the fast processor pipeline. Standard processor architectures implement two first-level caches to avoid a structural hazard in the pipeline: an instruction cache and a data cache. For tight worst-case execution times it is important to classify memory accesses as either cache hit or cache miss. The addresses of instruction fetches are known statically and static cache hit/miss classification is possible for the instruction cache. The access to data that is cached in the data cache is harder to predict statically. Several different data areas, such as stack, global data, and heap allocated data, share the same cache. Some addresses are known statically, other addresses are only known at runtime. With a standard cache organization all those different data areas must be considered by worst-case execution time analysis. In this paper we propose to split the data cache for the different data areas. Data cache analysis can be performed individually for the different areas. Access to an unknown address in the heap does not destroy the abstract cache state for other data areas. Furthermore, we propose to use a small, highly associative cache for the heap area. We designed and implemented a static analysis for this cache, and integrated it into a worst-case execution time analysis tool.

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“…Likewise, Manjikian et al [16] demonstrated a 25% reduction in execution time as a result of modifying the source-code of the executing software to use cache partitioning. Many optimization techniques [21,17,27] increase cache hit rate by enhancing source code to increase temporal locality of data accesses, which defines the proximity with which shared data is accessed in terms of time [13]. For example, loop interchange and loop fusion techniques can increase temporal locality of accessed data by modifying application source code to change the order in which application data is written to and read from a processor cache [13,16].…”

Section: Introductionmentioning

confidence: 99%

Optimizing Integrated Application Performance with Cache-Aware Metascheduling

Dougherty

White

Kegley

et al. 2011

On the Move to Meaningful Internet Systems: OTM 2011

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Abstract. Integrated applications running in multi-tenant environments are often subject to quality-of-service (QoS) requirements, such as resource and performance constraints. It is hard to allocate resources between multiple users accessing these types of applications while meeting all QoS constraints, such as ensuring users complete execution prior to deadlines. Although a processor cache can reduce the time required for the tasks of a user to execute, multiple task execution schedules may exist that meet deadlines but differ in cache utilization efficiency. Determining which task execution schedules will utilize the processor cache most efficiently and provide the greatest reductions in execution time is hard without jeopardizing deadlines. The work in this paper provides three key contributions to increasing the execution efficiency of integrated applications in multi-tenant environments while meeting QoS constraints. First, we present cache-aware metascheduling, which is a novel approach to modifying system execution schedules to increase cache-hit rate and reduce system execution time. Second, we apply cache-aware metascheduling to 11 simulated software systems to create 2 different execution schedules per system. Third, we empirically evaluate the impact of using cache-aware metascheduling to alter task schedules to reduce system execution time. Our results show that cache-aware metascheduling increases cache performance, reduces execution time, and satisfies scheduling constraints and safety requirements without requiring significant hardware or software changes.

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Timing predictability of cache replacement policies

Cited by 149 publications

References 7 publications

Selfish-LRU: Preemption-aware caching for predictability and performance

Selfish-LRU: Preemption-aware caching for predictability and performance

Data cache organization for accurate timing analysis

Optimizing Integrated Application Performance with Cache-Aware Metascheduling

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