Timing error statistics for energy-efficient robust DSP systems

Abdallah, Rami A.; Lee, Yu-Hung; Shanbhag, Naresh R.

doi:10.1109/date.2011.5763276

Cited by 6 publications

(2 citation statements)

References 14 publications

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“…Compared to this baseline, 8-bit LSB truncation (M[12, 8, 0]) produces a similarly low energy minimization curve, whereas 12-bit truncation (M[8, 12, 0]) results in a higher minimum energy curve. According to our experiments, 8-bit precision with less than 11-bit LSB truncation (i.e., M [8,8,4], M [8,9,3], and M[8, 10, 2]) achieve comparable energy minimization performance to the baseline precision (M[20, 0, 0]). However, other precisions, such as M [8,11,1] or M [7,8,5], perform worse due to large magnitude quantization or saturation errors.…”

Section: Verification Of Error Analysismentioning

confidence: 94%

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Error resilient MRF message passing architecture for stereo matching

Choi

Kim

Rutenbar

et al. 2013

SiPS 2013 Proceedings

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Message passing based inference algorithms have immense importance in real-world applications. In this paper, error resilience of a message passing based Markov random field (MRF) stereo matching architecture is explored and enhanced through application of algorithmic noise tolerance (ANT) in order to cope with nanometer imperfections in post-silicon devices. We first explore the inherent robustness of iteration based MRF inference algorithms. Analysis and simulations show that for a 20-bit architecture, small errors (e ≤ 1024) are tolerable, while large errors (e ≥ 4096) degrade the performance significantly. Based on these error characteristics, we propose an ANT architecture to effectively compensate for large magnitude circuit errors. Introducing timing errors via voltage over scaling (VOS), experimental results show that the proposed ANT based hardware can tolerate an error rate of 21.3 %, with performance degradation of only 0.47 % at a gate complexity overhead of 44.7 %, compared to an errorfree full precision hardware with an energy savings of 41 %.

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Section: Verification Of Error Analysismentioning

confidence: 94%

“…Such an additive error model has been shown to be realistic for timing errors in arithmetic computations [9]. An erroneous message for label 0,M st (0), can be represented as follows:…”

Section: Error Analysis Of Trw-smentioning

confidence: 99%