Timing-driven placement using design hierarchy guided constraint generation

Yang, Xiaojian; Choi, Bo-Kyung; Sarrafzadeh, Majid

doi:10.1145/774572.774598

Cited by 36 publications

(40 citation statements)

References 26 publications

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“…More recent publications (like [7] and [12]) using publicly available benchmarks only presented global placement results without any information about the amount of remaining overlap. Other works like [16], [10], and [9] used proprietary benchmarks to present results. Table 1 shows the comparison of [5] with our approach.…”

Section: Resultsmentioning

confidence: 99%

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Quadratic placement using an improved timing model

Obermeier

Johannes

2004

Proceedings of the 41st Annual Design Automation Conference

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The performance of timing-driven placement methods depends strongly on the choice of the net model. In this paper a more precise net model is presented that does not increase numerical complexity. We introduce a method that replaces the clique model of a net by a tree model in the quadratic placement formulation. This improvement enables us to control the length of every tree segment separately. Furthermore, we present an analysis of the effects of every tree segment to the net delay. The result is in turn used to control the placement engine. Our presented results are based on legal placements. They show significant improvements over state-of-the art methods.

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Section: Resultsmentioning

confidence: 99%

“…It has been used successfully for small designs. An advancement of this method is presented in [16]. The cluster stage has been replaced by a four-way hierarchical partitioning and the cost function is based on slack computation.…”

Section: Introductionmentioning

confidence: 99%

Quadratic placement using an improved timing model

Obermeier

Johannes

2004

Proceedings of the 41st Annual Design Automation Conference

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“…Net 1 connects cell 1 , cell 2 , cell 3 and cell 4 , net 2 connects cell 3 , cell 4 and cell 5 and net 3 connects cell 5 , cell 6 , cell 7 and cell 8 . Assume that the solution to the linear equations from Section 3 requires that the horizontal length of the bounding box of net 2 be reduced by 30%, with no reductions on net 1 and net 3 .…”

Section: Contraction Of the Critical Nets With Minimal Placement Changesmentioning

confidence: 99%

Incremental placement for timing optimization

Choi

Bazargan

2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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An incremental timing driven placement algorithm is presented. We introduce a fast path-based analytical approach for timing improvement. Our method achieves timing optimization by reducing the enclosing bounding boxes of selected nets on critical paths. Furthermore, this technique tries to minimize modifications to the initial placement while improving the delay of the circuit incrementally. Two contributions of this work are 1) efficient conversion of a path-based timing minimization problem to a geometric net-constraint problem and 2) minimal modification of a placement to improve timing. Our technique can take an initial placement from any algorithm and improve timing iteratively. The experiments show that the proposed approach is very efficient.

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“…Moreover, effective slack allocation is a hard problem for large circuits [7] (hence the need to iterate many times, each time changing the slack allocation.) Finally, running the timer again to check for the violations considering the number of instances in today's ICs is really time expensive and can increase the turn-around time for many days.…”

Section: Introductionmentioning

confidence: 99%

Post sign-off leakage power optimization

Abrishami

Lou

Qin

et al. 2011

Proceedings of the 48th Design Automation Conference

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With the scaling down of the CMOS technologies, leakage power is becoming an increasingly important issue in IC design. There is a trade-off between subthreshold leakage power consumption and clock frequency in the circuit; i.e., for higher performance, leakage power consumption must be sacrificed and vice versa. Meanwhile, timing analysis during synthesis and physical design is pessimistic, which means there are some slacks available to be traded for leakage power minimization. This power minimization can be done after the sign-off which is more accurate and realistic than if it is done before the sign-off. The available slack can be traded for leakage power minimization by footprint-based cell swapping and threshold voltage assignment. In this paper, we introduce our post sign-off leakage power optimization problem as a nonlinear mathematical program and solve it by using conjugate gradient (CG) method. We set up a novel transformation technique to manipulate the constraints of the optimization problem to be solved by CG. We show that by doing this optimization we can reduce the leakage power consumption by 34% on average in comparison with no power optimization after sign-off. All experiments are done on the real industrial designs.

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Timing-driven placement using design hierarchy guided constraint generation

Cited by 36 publications

References 26 publications

Quadratic placement using an improved timing model

Quadratic placement using an improved timing model

Incremental placement for timing optimization

Post sign-off leakage power optimization

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