Timing constraints for correct performance

Youssef, Habib; Shragowitz, Eugene

doi:10.1109/iccad.1990.129830

Cited by 38 publications

(25 citation statements)

References 11 publications

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“…In maximum delay budgeting, the objective is to maximize the value of an expression, which is a function of budgets associated with the nodes/edges in a graph. The most popular and efficient algorithm for delay budgeting is zeroslack algorithm (ZSA) [4], [5]. The solution is not optimal and can be far away from optimal result.…”

Section: Introductionmentioning

confidence: 99%

Optimal Integer Delay-Budget Assignment on Directed Acyclic Graphs

Bozorgzadeh

Ghiasi

Takahashi

et al. 2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Excess delay that each component of a design can tolerate under a given timing constraint is referred to as delay budget. Delay budgeting has been widely exploited to improve the design quality in VLSI CAD flow. The objective of the delay budgeting problem investigated in this paper is to maximize the total delay budget assigned to each node in a directed acyclic graph under a given timing constraint. Due to discreteness of the timing of the components in the libraries during design optimization flow, discrete solution for delay budgeting is essential. We present an optimal integer delay budgeting algorithm. We prove that the problem can be solved optimally in polynomial time. In addition, we look at different extensions of the delay budgeting problem, such as maximization of weighted summation of delay budgets assigned to the nodes with constraints on lower bound and upper bound on the delay budget allocated to each node. We prove that for both aforementioned extensions, our algorithm can produce an optimal integer solution in polynomial time. Our algorithm is generic and can be applied in different design tasks at different levels of abstraction. We applied our proposed optimal delay budgeting algorithm in library mapping during datapath synthesis on an FPGA platform ,using pre-optimized cores of FPGA libraries. For each application, we go through synthesis and place and route stages in order to obtain accurate results. Our optimal algorithm outperforms ZSA algorithm [4] in terms of area by ½¼± on average for all applications. In some applications, optimal delay budgeting can speedup runtime of place and route up to ¾ times.Index Terms-delay budgeting, timing constraint, core-based design implementations,integer programming.

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Section: Introductionmentioning

confidence: 99%

Optimal Integer Delay-Budget Assignment on Directed Acyclic Graphs

Bozorgzadeh

Ghiasi

Takahashi

et al. 2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…The main idea is to distribute slacks at the endpoints of each path (POs or inputs of memory elements) to constituent nets in the path such that a zeroslack solution is obtained [Nair et al 1989;Youssef and Shragowitz 1990;Chen et al 2000]. The original zero-slack algorithm (ZSA) [Nair et al 1989] assigns slacks based mainly on fanout factors.…”

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confidence: 99%

Large-scale circuit placement

Cong¹,

Shinnerl²,

Xie³

et al. 2005

ACM Trans. Des. Autom. Electron. Syst.

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Placement is one of the most important steps in the RTL-to-GDSII synthesis process, as it directly defines the interconnects, which have become the bottleneck in circuit and system performance in deep submicron technologies. The placement problem has been studied extensively in the past 30 years. However, recent studies show that existing placement solutions are surprisingly far from optimal. The first part of this tutorial summarizes results from recent optimality and scalability studies of existing placement tools. These studies show that the results of leading placement tools from both industry and academia may be up to 50% to 150% away from optimal in total wirelength. If such a gap can be closed, the corresponding performance improvement will be equivalent to several technology-generation advancements. The second part of the tutorial highlights the recent progress on large-scale circuit placement, including techniques for wirelength minimization, routability optimization, and performance optimization.

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“…The new slack allocation algorithm extends [4], [5], and [6] to consider short-path timing constraints as well as long-path timing constraints. It produces minimum delay budgets in addition to maximum delay budgets and introduces upper delay bounds to complement lower delay bounds.…”

Section: Short-path and Long-path Slack Allocationmentioning

confidence: 99%

“…The Iterative-Minimax-PERT algorithm [5] improves on ZSA by introducing a faster slack allocation algorithm. This algorithm defines weights that can be used to distribute slacks nonuniformly -connections with larger weights are allocated more slack.…”

Section: Slack Allocationmentioning

confidence: 99%