2006
DOI: 10.1109/ats.2006.261012
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Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects

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Cited by 121 publications
(54 citation statements)
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“…When comparing against patterns with maximum PSN effects without considering functional constraints, we can observe more than 14% less PSN effects on average for all benchmark circuits, and scan patterns for benchmark s15850 can result in up to 23% more power supply noises than our patterns that try to maximize PSN effects under functional constraints. This comparison indicates that it is crucial to take functional constraints into consideration when generating SDD test pat- Result in [6] Result of our method terns. Otherwise, circuits can be over-tested, leading to significant test yield loss.…”
Section: Resultsmentioning
confidence: 99%
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“…When comparing against patterns with maximum PSN effects without considering functional constraints, we can observe more than 14% less PSN effects on average for all benchmark circuits, and scan patterns for benchmark s15850 can result in up to 23% more power supply noises than our patterns that try to maximize PSN effects under functional constraints. This comparison indicates that it is crucial to take functional constraints into consideration when generating SDD test pat- Result in [6] Result of our method terns. Otherwise, circuits can be over-tested, leading to significant test yield loss.…”
Section: Resultsmentioning
confidence: 99%
“…In our method, however, we drop those undetected faults if and only if they are located on the path targeted in relevant transition justification, since we need to guarantee the dropped faults have been affected by sufficient PSN effects. Consequently, our solution generates more test patterns than [6]. We compare the pattern count between the two methods, as shown in the Fig.9.…”
Section: Resultsmentioning
confidence: 99%
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