Timing analysis enhancement for synchronous program

Raymond, Pascal; Maïza, Claire; Parent-Vigouroux, Catherine; Carrier, Fabienne; Asăvoae, Mihail

doi:10.1007/s11241-015-9219-y

Cited by 15 publications

(20 citation statements)

References 21 publications

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“…For the work in this paper, we have established a heuristic mapping for the AVR gcc compiler with only little difficulty, as explained later in Section 3.2. Other researchers have accomplished the same goal for different WCET-amenable processors [32,52] even under some optimization, suggesting that such a mapping usually can be established when only considering the timing.…”

Section: Wcet Analysis At Source Code Levelmentioning

confidence: 99%

Scalable and precise estimation and debugging of the worst-case execution time for analysis-friendly processors: a comeback of model checking

Becker¹,

Metta²,

Venkatesh³

et al. 2018

Int J Softw Tools Technol Transfer

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Estimating the Worst-Case Execution Time (WCET) of an application is an essential task in the context of developing real-time or safety-critical software, but it is also a complex and error-prone process. Conventional approaches require at least some manual inputs from the user, such as loop bounds and infeasible path information, which are hard to obtain and can lead to unsafe results if they are incorrect. This is aggravated by the lack of a comprehensive explanation of the WCET estimate, i.e., a specific trace showing how WCET was reached. It is therefore hard to spot incorrect inputs and hard to improve the worst-case timing of the application. Meanwhile, modern processors have reached a complexity that refutes analysis and puts more and more burden on the practitioner. In this article we show how all of these issues can be significantly mitigated or even solved, if we use processors that are amenable to WCET analysis. We define and identify such processors, and then we propose an automated tool set which estimates a precise WCET without unsafe manual inputs, and also reconstructs a maximum-detail view of the WCET path that can be examined in a debugger environment. Our approach is based on Model Checking, which however is known to scale badly with growing application size. We address this issue by shifting the analysis to source code level, where source code transformations can be applied that retain the timing behavior, but reduce the complexity. Our experiments show that fast and precise estimates can be achieved with Model Checking, that its scalability can even exceed current approaches, and that new opportunities arise in the context of "timing debugging".

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Section: Wcet Analysis At Source Code Levelmentioning

confidence: 99%

Scalable and precise estimation and debugging of the worst-case execution time for analysis-friendly processors: a comeback of model checking

Becker¹,

Metta²,

Venkatesh³

et al. 2018

Int J Softw Tools Technol Transfer

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“…Raymond et al [20] integrate an existing verification tool to check the improvement of the estimated WCET from high-level model to C, and then binary code. Our work not only is intended to complement theirs, but also focuses on vectorization now.…”

Section: ) Impact Of Vectorization On Wcetmentioning

confidence: 99%

Tracing Flow Information for Tighter WCET Estimation: Application to Vectorization

Puaut

Rohou

2015

2015 IEEE 21st International Conference on Embedded and Real-Time Computing Systems and Applications

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Real-time systems have become ubiquitous, and many play an important role in our everyday life. For hard real-time systems, computing correct results is not the only requirement. In addition, these results must be produced within pre-determined deadlines. Designers must compute the worstcase execution times (WCET) of the tasks composing the system, and guarantee that they meet the required timing constraints. Standard static WCET estimation techniques establish a WCET bound from an analysis of the machine code, taking into account additional flow information provided at source code level, either by the programmer or from static code analysis. Precise flow information helps produce tighter WCET bounds, hence limiting over-provisioning the system. However, flow information is difficult to maintain consistent through the dozens of optimizations applied by a compiler, and the majority of real-time systems simply do not apply any optimization.

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“…The idea of combining high-level semantic information with low-level binary analysis has also already been applied in e.g. [12,15].…”

Section: Future Workmentioning

confidence: 99%

“…The longest path in this case is {(1), (2), (3), (5)}. Infeasible paths can be excluded in IPET by adding constraints to the ILP formula [15,14]. In this paper, we use another approach with Satisfiability Modulo Theory (SMT) that allows to encode the program's semantics and its execution time.…”

Section: Introductionmentioning

confidence: 99%

WCET analysis in shared resources real-time systems with TDMA buses

Rihani

Moy

Maïza

et al. 2015

Proceedings of the 23rd International Conference on Real Time and Networks Systems

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International audiencePredictability is an important aspect in real-time and safety-critical systems, where non-functional properties – such as the timing behavior – have high impact on the system cor-rectness. As many safety-critical systems have a growing performance demand, simple, but outdated architectures are not sufficient anymore. Instead, multi-core systems are more and more popular, even in the real-time domain. To combine the performance benefits of a multi-core architecture with the required predictability, Time Division Multiple Access (TDMA) buses are often advocated. In this paper, we are interested in accesses to shared resources in such environments. Our approach uses SMT (Satisfiability Modulo Theory) to encode the semantics and execution time of the analyzed program in an environment with shared resources. We use an SMT-solver to find a solution that corresponds to the execution path with correct semantics and maximal execution time. We propose to model a shared bus with TDMA arbitration policy. Using examples, we show how the WCET estimation is enhanced by combining the semantics and the shared bus analysis in SMT

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Timing analysis enhancement for synchronous program

Cited by 15 publications

References 21 publications

Scalable and precise estimation and debugging of the worst-case execution time for analysis-friendly processors: a comeback of model checking

Scalable and precise estimation and debugging of the worst-case execution time for analysis-friendly processors: a comeback of model checking

Tracing Flow Information for Tighter WCET Estimation: Application to Vectorization

WCET analysis in shared resources real-time systems with TDMA buses

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