Timed verification of the generic architecture of a memory circuit using parametric timed automata

Chevallier, Remy; Encrenaz-Tiphene, Emmanuelle; Fribourg, Laurent; Xu, Weiwen

doi:10.1007/s10703-008-0061-x

Cited by 28 publications

(20 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…In this case, the constraint K 0 allows us to optimize some values of the typical data π 0 . This is useful, for example in order to safely relax some requirements on the environment of asynchronous circuits (see, e.g., [6]). In the SPSMALL case study, this allows us to safely optimize some nominal setup timing by 8 % (see [5]).…”

Section: Methodsmentioning

confidence: 99%

IMITATOR: A Tool for Synthesizing Constraints on Timing Bounds of Timed Automata

André

2009

Theoretical Aspects of Computing - ICTAC 2009

View full text Add to dashboard Cite

Abstract. We present here Imitator, a tool for synthesizing constraints on timing bounds (seen as parameters) in the framework of timed automata. Unlike classical synthesis methods, we take advantage of a given reference valuation of the parameters for which the system is known to behave properly. Our aim is to generate a constraint such that, under any valuation satisfying this constraint, the system is guaranteed to behave, in terms of alternating sequences of locations and actions, as under the reference valuation. This is useful for safely relaxing some values of the reference valuation, and optimizing timing bounds of the system. We have successfully applied our tool to various examples of asynchronous circuits and protocols. ContextTimed automata [1] are finite control automata equipped with clocks, which are real-valued variables which increase uniformly. This model is useful for reasoning about real-time systems, because one can specify quantitatively the interval of time during which the transitions can occur, using timing bounds. However, the behavior of a system is very sensitive to the values of these bounds, and it is rather difficult to find their correct values. It is therefore interesting to reason parametrically, by considering that these bounds are unknown constants, or parameters, and try to synthesize a constraint (i.e., a conjunction of linear inequalities) on these parameters which will guarantee a correct behavior of the system. Such automata are called parametric timed automata (PTA) [2,11].The synthesis of constraints for PTA has been mainly done by supposing given a set of "bad states" (see, e.g., [8,9]). The goal is to find a set of parameters for which the considered timed automaton does not reach any of these bad states. We call such a method a bad-state oriented method. By contrast, we present in this paper a tool based on a good-state oriented method. Principle of ImitatorThe tool Imitator (Inverse Method for Inferring Time AbstracT behaviOR) implements the algorithm InverseMethod , described in [4]. We assume given a

show abstract

Section: Methodsmentioning

confidence: 99%

IMITATOR: A Tool for Synthesizing Constraints on Timing Bounds of Timed Automata

André

2009

Theoretical Aspects of Computing - ICTAC 2009

View full text Add to dashboard Cite

show abstract

“…Beyond the usual academic examples (such as variants of train controllers [AHV93; Hun+02]), PTAs were also used to successfully specify and verify numerous interesting case studies such as the root contention protocol [Hun+02], Philip's bounded retransmission protocol [Hun+02], a 4-phase handshake protocol [KP12], the alternating bit protocol [JLR15], an asynchronous circuit commercialized by ST-Microelectronics [Che+09], (non-preemptive) schedulability problems [JLR15], a distributed prospective architecture for the flight control system of the next generation of spacecrafts designed 5 https://embedded.eecs.berkeley.edu/research/hytech/ at ASTRIUM Space Transportation [Fri+12], an unmanned aerial video system by Thales 6 , and even analysis of music scores [FJ13].…”

Section: Applicationsmentioning

confidence: 99%

What’s decidable about parametric timed automata?

André

2017

Int J Softw Tools Technol Transfer

View full text Add to dashboard Cite

Parametric timed automata (PTAs) are a powerful formalism to reason, simulate and formally verify critical real-time systems. After 25 years of research on PTAs, it is now well-understood that any non-trivial problem studied is undecidable for general PTAs. We provide here a survey of decision and computation problems for PTAs. On the one hand, bounding time, bounding the number of parameters or the domain of the parameters does not (in general) lead to any decidability. On the other hand, restricting the number of clocks, the use of clocks (compared or not with the parameters), and the use of parameters (e. g., used only as upper or lower bounds) leads to decidability of some problems. We also put emphasis on open problems. We also discuss formalisms close to parametric timed automata (such as parametric hybrid automata or parametric interrupt timed automata), and we study tools dedicated to PTAs and their extensions.

show abstract

“…The SPSMALL case study corresponds to an asynchronous memory sold by ST-Microelectronics, and studied in the framework of VALMEM project. We considered two versions of this case study: the first one ("SPSMALL 1 ") was manually abstracted from the VHDL code (see [11]) and several gates have been merged into a single PTA. The second model ("SPSMALL 2 ") has been automatically generated from the VHDL code without any simplification.…”

Section: Case Studiesmentioning

confidence: 99%

IMITATOR II: A Tool for Solving the Good Parameters Problem in Timed Automata

André¹

2010

Electron. Proc. Theor. Comput. Sci.

View full text Add to dashboard Cite

We present here IMITATOR II, a new version of IMITATOR, a tool implementing the "inverse method" for parametric timed automata: given a reference valuation of the parameters, it synthesizes a constraint such that, for any valuation satisfying this constraint, the system behaves the same as under the reference valuation in terms of traces, i.e., alternating sequences of locations and actions. IMITA-TOR II also implements the "behavioral cartography algorithm", allowing us to solve the following good parameters problem: find a set of valuations within a given bounded parametric domain for which the system behaves well. We present new features and optimizations of the tool, and give results of applications to various examples of asynchronous circuits and communication protocols.

show abstract

Timed verification of the generic architecture of a memory circuit using parametric timed automata

Cited by 28 publications

References 12 publications

IMITATOR: A Tool for Synthesizing Constraints on Timing Bounds of Timed Automata

IMITATOR: A Tool for Synthesizing Constraints on Timing Bounds of Timed Automata

What’s decidable about parametric timed automata?

IMITATOR II: A Tool for Solving the Good Parameters Problem in Timed Automata

Contact Info

Product

Resources

About