Timed Path Conditions in MATLAB/Simulink

Abstract

MATLAB/Simulink is a widely-used industrial tool for the development of complex embedded systems. However, due to the complexity and the dynamic character of the developed models, their analysis is a difficult challenge, in particular if timing aspects are involved. In this paper, we present an approach for the construction of timed path conditions for MATLAB/Simulink models. Timed path conditions allow for fine-grained conclusions about the existence of possibly critical paths through a model containing time-dependent elements. With the help of timed path conditions, it is possible to identify interference and noninterference between model parts. Furthermore, they have the potential to reduce the complexity of models to improve verifiability, reason about compliance with security policies as well as generate feasible, efficient test cases. We demonstrate the applicability of our approach with a shared buffer for public as well as confidential data.

Information Flow Analysis of Combined Simulink/Stateflow Models

“…(1) We utilize our algorithm shown in [18,19] to extract timed path conditions for all paths between a elements of interest from the Simulink model (see step (1.a) in Figure 4). Along these paths, th for information flow as well as their timing are gathered and expressed as sets of timed path con To make this representation compatible with the UPPAAL timed automata representation of th semantics presented in [19], we propose a timed automata representation of these timed pat tion rules that determine which transition fires in each step, whereby a step is made whenever one of the input signals is reevaluated, i. e., every simulation time step t s .…”

“…The main idea of our approach for the analysis of the information flow in combined, discrete Simulink/Stateflow models is to relate a Stateflow controller with its surrounding Simulink model using timed automata in order to enable model checking. For the analysis of information flow in pure Simulink components, we make use of our approach previously presented in [18]. There, we compute timed path conditions for a given Simulink model by performing a backwards analysis through the model.…”

“…To relate the timed path conditions resulting from [18] for Simulink components with the UPPAAL timed automata representation of Stateflow components, we assume that a Stateflow controller is embedded into a Simulink model and has an effect on some of its components by controlling the execution of paths through the surrounding Simulink components. Our approach to analyze the information flow in combined Simulink/ Stateflow models, shown in Figure 4, is threefold:…”

“…1 We utilize our algorithm shown in [18,19] to extract timed path conditions for all paths between a set of model elements of interest from the Simulink model (see step (1.a) in Figure 4). Along these paths, the conditions for information flow as well as their timing are gathered and expressed as sets of timed path conditions C TP .…”

“…1 Only time-discrete, fixed-step solvers are used [18], All discrete Simulink/Stateflow models that satisfy these assumptions can be safely analyzed using our approach. Note that as we analyze the control flow of Simulink subsystems, we do not impose any restrictions on the data paths, i. e., complex modeling elements like integrators and transfer functions, together with arbitrary feedback loops, may be used on the data path.…”