Time-predictable code execution — Instruction-set support for the single-path approach

Abstract

When designing modern real-time systems, which have to deliver results at specified deadlines, knowing the worst-case execution time (WCET) of software components is of utmost importance. Although there has been much research in the field of WCET analysis in the last years, with a focus on improving the accuracy of processor models and WCET-calculation methods, researchers have paid little attention to exploring the impact of the instruction set architecture (ISA) on the time predictability of the code executing on a given real-time processor. In this paper we explore ISA extensions that allow compilers to generate highly time-predictable code. To this end, an existing instruction set has been extended by a number of instructions, and the LLVM compiler framework has been adapted to use these new instructions in its assembler-code generator. The timing behavior of the generated code has been evaluated by means of an instruction-set simulator. The results of the experiments allowed us to identify a promising combination of the newly introduced instructions. The use of these instructions leads to a reduction of the number of branches in the assembler code, thus improving time predictability while still providing competitive worst-case timing.

A Generator for Time-Predictable Code

“…A set of rules describes how to transform a piece of code given in a high-level representation to a singlepath version was presented in [7]. The influence of selected instruction-set extensions, specifically suitable for single-path conversion at assembly level, both on execution time and code size was investigated in [8], where the study was performed on code examples already written in a WCET-oriented fashion.…”