Time optimization of instruction execution in FPGA using embedded systems

Abstract

This paper presents a method to implement time optimization of instructions in Field Programmable Gate Array (FPGA) using application of embedded systems. The proposed technique is intended to reduce the time of processing of instructions inside a processor and ATMega328 microcontroller is used for this purpose. An algorithm has been proposed to predict the most suitable processor architecture which should be preferably used to iteratively execute the instructions. This prediction, along with the input of instructions to the FPGA, is done by the microcontroller and the same is transferred to the FPGA using suitable interfacing technique. Two architectures are intertwined and burnt on the microprocessor chip of the FPGA beforehand. Proteus VSM has been used for simulation of the embedded portion of the system and the processor architectures are designed in Xilinx ISE v13.4 and simulated in ISIM simulator.

Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer

“…Other techniques reconfigure cache using computer software [43], while some techniques predict the program behaviour [3,41,42,[44][45][46]. Some techniques deal with instructions in the cache [3,15,16,41,[47][48][49][50][51][52]. Some techniques seek to leverage unused cache block words in order to reduce dynamic power consumption [18,36,53].…”

A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption

“…The oscillator is then matched to a temperature-compensated onchip resistor using an ultra-low power amplifier. A test chip is fabricated in 0.18µm CMOS that exhibits a temperature sufficient of 34.3ppm/degrees Celsius with long-term stability of less than 7ppm.Yen et al [72] discuss a low store energy and robust ReRAM-Based flip-flop for normally-off microprocessors. The technique of Normally-of Computing (NoC) benefits microsystems with long sleep time.…”