Time interleaved converter arrays

Black, W.C.; Hodges, D.A.

doi:10.1109/isscc.1980.1156111

Cited by 193 publications

(226 citation statements)

References 4 publications

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“…Figure 4.18 shows the block diagram of an architecture in which four ADCs are used in parallel to achieve four times the sampling rate of a single converter. This is often known as time-interleaved architecture [92], since the operation of the ADC channels is interleaved in such a way that one channel processes every fourth sample. The digital outputs of the channels are combined with a multiplexer to a single full-speed bitstream.…”

Section: Calibrationmentioning

confidence: 99%

“…The channels may have different offset voltages, their absolute gains can be different, or there can be a constant skew in the clock signals [92]. How these errors are seen in the spectrum of the sampled signal will be discussed in conjunction with the doublesampling technique in Chapter 9.…”

Section: Problems and Solutionsmentioning

confidence: 99%

“…Parallel pipeline ADCs with several time-interleaved component ADCs have been introduced to attain very high sampling rates with acceptable power consumption [93,92]. A resolution of ten bits and conversion rates up to 100 MS/s have been reported [98].…”

Section: -Bit 200-ms/s Parallel Pipeline Adcmentioning

confidence: 99%

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Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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Section: Calibrationmentioning

confidence: 99%

Section: Problems and Solutionsmentioning

confidence: 99%

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Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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“…So multiple-core architectures with time-interleaved can be used to increase sample rates [1]. But the capability of digitizing signals with bandwidths needs to accord with the sample rates.…”

Section: Introductionmentioning

confidence: 99%

A 1.8V 12-bit 1GS/s SiGe BiCMOS time-interleaved Analog-to-Digital converter

Xu¹,

Li²,

Shen³

et al. 2015

Proceedings of the 3rd International Conference on Material, Mechanical and Manufacturing Engineering

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Abstract. This paper describes a 1.8V 12 bit 1 GS/s pipeline ADC realized in a 0.18 μm BiCMOS SiGe process. The ADC consists of a two-way time-interleaved hierarchical structure. Each sub-ADC consists of one input buffer and T&H with BiCMOS technology which improves the dynamic performance and reduces the converter error rate. The interleaving spurs caused by channel mismatch use OTPNVM to recode calibration. It achieves an SFDR of 87dB at 200MHz. Spectre simulation shows that the spurs of the channel mismatch achieve less than -106dB at gain and timing error, -97dB at the offset error.

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“…Time-interleaving multiple analog-to-digital converters (ADCs) [1] is a widely used approach to accommodate the demand for higher sampling rates combined with high accuracy and low power consumption. For example, in Figure 1 p parallel ADCs, each with a separate track-and-hold (T&H) circuit, are combined to compose a p times faster ADC: each T&H samples the same input signal V in with the same sample rate f s / p, but the samples are taken at different phases of the clock, such that after digital recombination, the overall system behaves as a single ADC operating at f s .…”

Section: Introductionmentioning

confidence: 99%

Analog calibration of channel mismatches in time‐interleaved ADCs

Harpe

Hegt

Roermund

2008

Circuit Theory & Apps

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SUMMARYThis paper presents a method for the on-chip measurement and correction of gain errors, offsets and time-skew errors in time-interleaved ADCs. With the proposed method, the errors can be measured and processed in the digital domain. Then, this information is used to optimize several digitally controlled analog parameters of the circuit, which minimize the effect of aforementioned mismatch errors. After optimization, the digital logic can be switched off completely in order to save power. Simulation results on a full-transistor implementation of the time-interleaved sampling structure show that the channel matching errors can be accurately compensated.

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Time interleaved converter arrays

Cited by 193 publications

References 4 publications

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

A 1.8V 12-bit 1GS/s SiGe BiCMOS time-interleaved Analog-to-Digital converter

Analog calibration of channel mismatches in time‐interleaved ADCs

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