Time Constrained Verification of Analog Circuits using Model-Checking Algorithms

Grabowski, Darius; Platte, Daniel; Hedrich, Lars; Barke, Erich

doi:10.1016/j.entcs.2006.01.026

Cited by 19 publications

(17 citation statements)

References 6 publications

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“…The generated test case shows that after the transient time, under a timevariant deviation of C 2 which ranges within ±10% of the value of C 2 = 0.1e−4, the variables v C 1 and v C 2 oscillate with the period T ∈ [1.25, 1.258]s (with ε = 2.8e − 4). This result is consistent with the result presented in [19]. The number of generated states was 30000 and the computation time was 14 minutes.…”

Section: Analog and Mixed-signal Circuitssupporting

confidence: 82%

See 1 more Smart Citation

How to Design Extended Finite State Machine Test Models in Java

Utting¹

2017

Model-Based Testing for Embedded Systems

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Section: Analog and Mixed-signal Circuitssupporting

confidence: 82%

“…Voltage controlled oscillator. The second circuit we examined is a voltage controlled oscillator (VCO) circuit [19], described by a system of DAEs with 55 continuous variables.…”

Section: Analog and Mixed-signal Circuitsmentioning

confidence: 99%

How to Design Extended Finite State Machine Test Models in Java

Utting¹

2017

Model-Based Testing for Embedded Systems

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“…There is no standard method for partitioning the state space, and therefore it seems to be complicated to find proper discrete models for strongly nonlinear models. In [23][24][25] focus is on nonlinear analog behavior for which discretized models in the state space are used for verification. The efficiency of these approaches seems to be limited to smaller analog systems.…”

Section: State Of Art and Related Workmentioning

confidence: 99%

Verification of Mixed-Signal Systems with Affine Arithmetic Assertions

et al. 2013

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Embedded systems include an increasing share of analog/mixed-signal components that are tightly interwoven with functionality of digital HW/SW systems. A challenge for verification is that even small deviations in analog components can lead to significant changes in system properties. In this paper we propose the combination of range-based, semisymbolic simulation with assertion checking. We show that this approach combines advantages, but as well some limitations, of multirun simulations with formal techniques. The efficiency of the proposed method is demonstrated by several examples.

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“…Many methods had been proposed for this. For instance, the model checking of analog circuits for the specification of time constraints was discussed [17], an approach of defining time-based specifications was introduced. For the verification of mixed-signal circuits, the behavioral description of the mixed-signal circuit was transformed into a discrete model [18], and the verification was performed by formal digital verification technique.…”

Section: Introductionmentioning

confidence: 99%

Determining Equivalent Signal Lines by Weight Value Assignment for Logic Verification of Digital Circuits

Zhang

Ling²,

Chen³

2014

TOEEJ

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Abstract:The VLSI technology has led to the increased complexity in hardward design, therefore the verification for the correctness of circuit operations has become an exrtremely important task. The verification procedure can be reduced by means of the equivalent signal lines in the circuits. In this paper, a new method is presented for determining the equivalent signal lines, the method utilizes the weight value assignment of signal lines in circuits. First of all, the method makes use of the topological information of circuits to perform forward weight value assignments, assign weight values to the signal lines from the primary inputs to primary outputs. Afterwards, carry out the backward weight value assignment, assign weight values to the signal lines from the primary outputs to primary inputs. Secondly, carry out the random pattern simulation to further check the equivalence of signal lines. A lot of experimental results show that the verification of digital circuits can be carried out effectively by using the method proposed in this paper, the time being needed for the verification procedure can be cut down by utilizing the equivalent signal lines.

show abstract

Time Constrained Verification of Analog Circuits using Model-Checking Algorithms

Cited by 19 publications

References 6 publications

How to Design Extended Finite State Machine Test Models in Java

How to Design Extended Finite State Machine Test Models in Java

Verification of Mixed-Signal Systems with Affine Arithmetic Assertions

Determining Equivalent Signal Lines by Weight Value Assignment for Logic Verification of Digital Circuits

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