Time-constrained code compaction for DSPs

Abstract

This paper addresses instruction-level parallelism in code generation for DSPs. In presence of potential parallelism, the task of code generation includes code compaction, which parallelizes primitive processor operations under given dependency and resource constraints. Furthermore, DSP algorithms in most cases are required to guarantee real-time response. Since the exact execution speed of a DSP program is only known after compaction, real-time constraints should be taken into account during the compaction phase. While previous DSP code generators rely on rigid heuristics for compaction, we propose a novel approach to exact local code compaction based on an Integer Programming model, which handles time constraints. Due to a general problem formulation, the IP model also captures encoding restrictions and handles instructions having alternative encodings and side e ects, and therefore applies to a large class of instruction formats. Capabilities and limitations of our approach are discussed for di erent DSPs.

An efficient model for DSP code generation: performance, code size, estimated energy

“…In combination with our addressing technique the savings in performance and codes size is even more significant, see table 4. For example in the cmul case the acutal final code using indirect addressing provides improvement over what was reported as the theoretical lower bound in [11].…”

“…All the code generated using the technique described in this paper has been verified through simulation with TI compiler generated code. The cmul example was taken from [11] and the dfg example was taken from [2]. The lms is a least means square algorithm and the hp1 and hp2 are high pass filter in direct form I and direct form II.…”

“…For example the cmul example is that shown in figure 2 which uses 10 instructions (without counting indirect addressingrelated instructions). The sequence of operations used for the cmul example is same as that used in [11] in order to compare with their code compaction technique which required 12 instructions. Table 3 shows the size of the ILP models and the cpu times required to generate the solutions.…”

“…To illustrate the model performance the extension to simultaneous scheduling, instruction selection, register allocation and compaction was performed for the cmul example in only 2.3 cpu seconds, see second last row of table 3 (after searching through several nodes of the branch and bound tree). The code compactor in [11] (which does not perform instruction selection and register allocation) uses an ILP solution and runs on a RS/6000. A final run was also performed to see if the optimization model could improve upon the result of the sequencing of operations to optimize performance.…”

“…The high level language describing the application is decomposed into a series of basic blocks which are then optimized through the code generation model for performance, code size and finally estimated power. After the code is generated (which assumes direct memory addressing), the data layout is performed using existing [13] or extended techniques [11] followed by an optimization approach to address generation (using auxiliary registers) such as [12]. In this paper for illustration purposes we will use the TMS320C2x processor as the target processor.…”