Throughput regulation in multicore processors via IPA

Almoosa, Nawaf; Song, Won Kyung; Yalamanchili, Sudhakar; Wardi, Yoraı̈

doi:10.1109/cdc.2012.6426610

Cited by 12 publications

(17 citation statements)

References 23 publications

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“…The plant is modelled as a discrete event dynamic system controlled by the processor's clock rate (frequency), whose output is the average instruction-throughput measured over short time frames. The technique was verified by both simulation [19], [20] and implementation on a Haswell machine [22]. In simulation the derivative term…”

Section: Power Regulation Techniquementioning

confidence: 97%

“…Subsequently it has been analyzed in an abstract setting in [18], where its convergence, stability, and robustness were proved. Its performance was tested via simulation on instruction-throughput regulation [19], [20], then on throughput of abstract Discrete Event Dynamic Systems (DEDS) such as queues, Petri nets and transportation networks [21]. Lately the controller has been implemented on Intel's fourthgeneration micro-architecture, Haswell [22], where it was tested on instruction-throughput regulation.…”

Section: Introductionmentioning

confidence: 99%

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Power regulation in high performance multicore processors

Chen

Wardi

Yalamanchili

2017

2017 IEEE 56th Annual Conference on Decision and Control (CDC)

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This paper presents, implements, and evaluates a power-regulation technique for multicore processors, based on an integral controller with adjustable gain. The gain is designed for wide stability margins, and computed in real time as part of the control law. The tracking performance of the control system is robust with respect to modeling uncertainties and computational errors in the loop. The main challenge of designing such a controller is that the power dissipation of program-workloads varies widely and often cannot be measured accurately; hence extant controllers are either ad hoc or based on a-priori modeling characterizations of the processor and workloads. Our approach is different. Leveraging the aforementioned robustness it uses a simple textbook modeling framework, and adjusts its parameters in real time by a system-identification module. In this it trades modeling precision for fast computations in the loop making it suitable for on-line implementation in commodity data-center processors. Consequently, the proposed controller is agnostic in the sense that it does not require any a-priori system characterizations. We present an implementation of the controller on Intel's fourth-generation microarchitecture, Haswell, and test it on a number of industry benchmark programs which are used in scientific computing and datacenter applications. Results of these experiments are presented in detail exposing the practical challenges of implementing provably-convergent power regulation solutions in commodity multicore processors.

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Section: Power Regulation Techniquementioning

confidence: 97%

Section: Introductionmentioning

confidence: 99%

Power regulation in high performance multicore processors

Chen

Wardi

Yalamanchili

2017

2017 IEEE 56th Annual Conference on Decision and Control (CDC)

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“…The regulation technique was extensively tested on programs from an industry-based suite of benchmarks, Splash-2 [7], using a detailed simulation platform for performance assessment of computer architectures, Manifold [8]. We reported the results in [2], [6], [9], and deemed them encouraging and meriting a further exploration of the regulation technique.…”

Section: Introductionmentioning

confidence: 98%

“…Second, much of the research of IPA has focused on its unbiasedness, whereas here, in contrast, the concern is with fast computation which may come at the expense of accuracy and unbiasedness. The main novelty of the paper as compared to References [2], [6], [9] is in the fact that it concerns not simulation but an actual implementation. In this we were facing new challenges associated with real-time measurements, computations, and control.…”

Section: Introductionmentioning

confidence: 99%

“…In this we were facing new challenges associated with real-time measurements, computations, and control. Consequently we were unable to control each core separately as in [2], [6], [9], and hence applied the regulation method to a processor containing multiple cores. Furthermore, due to issues with real-time computation, we were forced to take drastically cruder approximations to the IPA derivatives than in [2], [6], [9], and in fact it seems that we drove the degree of imprecision to the limit.…”

Section: Introductionmentioning

confidence: 99%

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IPA in the loop: Control design for throughput regulation in computer processors

Chen

Wardi

Yalamanchili

2016

2016 13th International Workshop on Discrete Event Systems (WODES)

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A new technique for performance regulation in event-driven systems, recently proposed by the authors, consists of an adaptive-gain integral control. The gain is adjusted in the control loop by a real-time estimation of the derivative of the plant-function with respect to the control input. This estimation is carried out by Infinitesimal Perturbation Analysis (IPA). The main motivation comes from applications to throughput regulation in computer processors, where to-date, testing and assessment of the proposed control technique has been assessed by simulation. The purpose of this paper is to report on its implementation on a machine, namely an Intel Haswell microprocessor, and compare its performance to that obtained from cycle-level, full system simulation environment. The intrinsic contribution of the paper to the Workshop on Discrete Event System is in describing the process of taking an IPA-based design and simulation to a concrete implementation, thereby providing a bridge between theory and applications.

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