Threshold voltage model for small geometry AlGaN/GaN HEMTs based on analytical solution of 3-D Poisson's equation

Kumar, Sachin; Agrawal, Ajay; Chaujar, Rishu; Kabra, Sneha; Gupta, Mridula; Gupta, R. S.

doi:10.1016/j.mejo.2007.09.001

Cited by 28 publications

(13 citation statements)

References 9 publications

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“…In conventional AIGaN/GaN HEMT devices, threshold voltage becomes more negative as width becomes narrow [14] and reverse is observed for the trig ate HEMT as width is reduced [5], [7], [13]. The difference in the behavior of the threshold voltage with respect to channel width (as width becomes narrow), indicates that we need different model for the trigate as compared to the conventional planar HEMT.…”

Section: Model Descriptionmentioning

confidence: 99%

Threshold voltage modeling of GaN based normally-off tri-gate transistor

Yadav

Kushwaha

Agarwal

et al. 2014

2014 Annual IEEE India Conference (INDICON)

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In this paper, a behavioral model of threshold voltage for normally-off (enhancement mode) AIGaN/GaN based tri-gate HEMT is proposed. AIGaN/GaN based tri-gate HEMT devices have additional sidewall gates and show threshold voltage variation with decreasing device width. The proposed model captures strain relaxation with reduction in device width , which is one of the primary reason for change in vt h in AIGaN/GaN tri-gate devices. Model shows excellent agreement with state-of the-art experimental and simulation data.

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Section: Model Descriptionmentioning

confidence: 99%

Threshold voltage modeling of GaN based normally-off tri-gate transistor

Yadav

Kushwaha

Agarwal

et al. 2014

2014 Annual IEEE India Conference (INDICON)

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“…have attracted attention in satellite communications, in optical communication systems and in mobile communications, due to their high-power performance.The most effective way to increase the circuit performance is to reduce their size, which will greatly benefit in satellite communications and broadband wireless communications.As scaling technologies has drawn our attention towards reducing the channel length and increasing the performance of the device, its results in serious drawbacks of Short Channel Effects (SCEs) [5].…”

Section: Hemtsmentioning

confidence: 99%

A Novel scaling theory for Single Gate AlInSb/InSb High Electron Mobility Transistors

LakshmiPriya

Manikandan

Balamurugan

et al. 2014

2014 International Conference on Communication and Network Technologies

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A Novel scaling theory for Single Gate AlInSb/InSb High Electron Mobility Transistors (HEMTs)is derived by solving the 2D Poisson equation. To combat with the issues introduced by device scaling,Effective Conductive Path Effect (ECPE) has been taken into account.From literature, scaling Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)with ECPE has shown stronger immunity towards short channel effects (SCEs). Hence, on introducing the ECPE in HEMT, a simple scaling equation has been derived and on solving this equation deff,min and behavior of high electron mobility transistors. The analytical model has been further extended in finding the various device parameters. Then simulations of the proposed work are performed using 2D TCAD sentaurus device simulator. The analytical results are compared and verified with the TCAD simulation results. Finally, results of the proposed work are compared with the scaling theory for MOSFETs with ECPE.

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“…Nano-scaling of metal oxide semiconductor field effect transistors (MOSFETs) has recently been great interest in research activities of CMOS technology to continuously develop the devices more smaller, faster and consume less power for the same level of integration [1][2]. In purpose of increasing ON-state current for better performance the gate length (LG) needs to be shrinked.…”

Section: Introductionmentioning

confidence: 99%

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

Faisal¹,

Hasan²,

Hossain³

et al. 2017

CCS Archive

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GaN-based double gate metal-oxide semiconductor fieldeffect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green's function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, V GS =1 V while it is going to off at V GS = 0 V. The ON-state and OFFstate drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, V DS = 0.75 V. The subthreshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (L UN ). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

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Threshold voltage model for small geometry AlGaN/GaN HEMTs based on analytical solution of 3-D Poisson's equation

Cited by 28 publications

References 9 publications

Threshold voltage modeling of GaN based normally-off tri-gate transistor

Threshold voltage modeling of GaN based normally-off tri-gate transistor

A Novel scaling theory for Single Gate AlInSb/InSb High Electron Mobility Transistors

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

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