Threshold Voltage Instability of Enhancement-Mode GaN Buried <i>p</i>-Channel MOSFETs

Zheng, Zheyang; Zhang, Li; Song, Wenlei; Chen, Tao; Feng, Sirui; Ng, Yat Hon; Sun, Jiahui; Han, Xu; Yang, Song; Wei, Jin

doi:10.1109/led.2021.3114776

Cited by 21 publications

(13 citation statements)

References 26 publications

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“…However, at the Al 2 O 3 /p-GaN interface, a large number of trap states would be charged by holes at high gate bias. The trapped holes would deplete part of the holes in the p-FET channel, resulting in the reduction of the channel current [38]. As a consequence, in the conventional Al 2 O 3 -gate device, the g m drops greatly with V GS < -5 V. To eliminate the influence of trap states in the gate region, a dielectric that has type-II alignement with p-GaN, such as SiN x in this demonstration, can be chosen.…”

Section: Device-level Demonstration: Diodes and P-fetsmentioning

confidence: 99%

Section: Device-level Demonstration: Diodes and P-fetsmentioning

confidence: 99%

“…In our previous works [8,[38][39][40], we have discussed other advantages of this unique GaON nanolyer in boosting the performance of GaN p-FETs. For example, the threshold voltage instability caused by interface trap states in conventional Al 2 O 3 -gate devices can also be greatly suppressed by this novel GaON/SiN x gate stack [38,39]. Meanwhile, in GaN p-FETs, as junctionless devices, gate-recess is an intuitive way to realize normally-OFF operation [41], while the etching-induced damages would decrease the hole mobility in the channel of p-FETs, as the channel is very close to the etched interface.…”

Section: Device-level Demonstration: Diodes and P-fetsmentioning

confidence: 99%

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Lattice-aligned gallium oxynitride nanolayer for GaN surface enhancement and function extension

Chen¹,

Zhao²,

Feng³

et al. 2022

Preprint

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Gallium nitride (GaN), as a promising alternative semiconductor to silicon, is of well-established use in photoelectronic and electronic technology. However, the vulnerable GaN surface has been a critical restriction that hinders the development of GaN-based devices, especially regarding device stability and reliability. Here, we overcome this challenge by converting the GaN surface into a gallium oxynitride (GaON) epitaxial nanolayer through an in-situ two-step "oxidation-reconfiguration" process. The oxygen plasma treatment overcomes the chemical inertness of the GaN surface, and the sequential thermal annealing manipulates the kinetic-thermodynamic reaction pathways to create a metastable GaON nanolayer with wurtzite lattice. This GaN-derived GaON nanolayer is a tailored structure for surface reinforcement and possesses several advantages, including wide bandgap, high thermodynamic stability, and large valence band offset with GaN substrate. These enhanced physical properties can be further leveraged to enable GaN-based applications in new scenarios, such as complementary logic integrated circuits, photoelectrochemical water splitting, and ultraviolet photoelectric conversion, making GaON a versatile functionality extender. * Junting Chen and Junlei Zhao contributed equally to this work.

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Section: Device-level Demonstration: Diodes and P-fetsmentioning

confidence: 99%

Section: Device-level Demonstration: Diodes and P-fetsmentioning

confidence: 99%

Section: Device-level Demonstration: Diodes and P-fetsmentioning

confidence: 99%

See 1 more Smart Citation

Lattice-aligned gallium oxynitride nanolayer for GaN surface enhancement and function extension

Chen¹,

Zhao²,

Feng³

et al. 2022

Preprint

Self Cite

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“…One elementary component of the proposed memory is a GaN p-channel field-effect transistor (p-FET) [21]. The Al2O3/p-GaN (i.e., blocking oxide/channel) interface is used as the CSL, where high-density interfacial trap states are created to induce significant threshold voltage (VTH) variation [22]. The p-channel that serves as a path for hole injection is separated from the CSL by a p-GaN depletion region (the first junction, termed as J1), as shown in Fig.…”

Section: Device Structure and Operation Principlementioning

confidence: 99%

GaN Non-Volatile Memory Based on Junction Barrier-Controlled Bipolar Charge Trapping

Chen

Zheng

Feng

et al. 2022

IEEE Electron Device Lett.

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A tunnel-oxide-free GaN-based non-volatile memory (NVM) device is proposed to untangle the trilemma among speed, retention, and endurance in the implementation of conventional NVM. The program and erase (P/E) are based on bipolar charge injection controlled by individual junction barriers, whereas the data retention relies on bipolar charge trapping in an interfacial charge storage layer. The wide bandgap energy of GaN allows the formation of deep-level traps at a dielectric/GaN interface and high junction barriers in GaN, both of which benefit long-term retention. As such, the GaN-based NVM device could get rid of the tunnel oxide, thereby enabling faster P/E processes and facilitating to decouple the enhancement of endurance from that of speed and retention. The proposed device demonstrates a P/E time of 100 ns, endurance over 10 6 cycles, and long retention time.

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“…Oxygen plasma treatment (OPT) prior to gate dielectric deposition leads to E-mode p-FETs with reasonable I ON and high I ON /I OFF ratio [14]. However, the oxide/ p-GaN interface could have a high density of trap states [19], [20], resulting in threshold voltage (V TH ) instability in oxide/ p-GaN-based gate stacks [21], [22]. The V TH could be effectively stabilized by upgrading the OPT technique to form an in-situ gallium oxynitride (GaON) layer on the recessed p-GaN surface and using silicon nitride (SiN x ) as the gate dielectric [23].…”

mentioning

confidence: 99%

Gate Leakage and Reliability of GaN -Channel FET With SiNₓ/GaON Staggered Gate Stack

Zhang
¹
,

Zheng
²
,

Song
³

et al. 2022

IEEE Electron Device Lett.

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p-channel GaN field-effect transistors (FETs) with a SiN x /GaON gate stack have been demonstrated with enhanced stability within a wide range of voltage bias and temperature. In this letter, the gate leakage characteristics and reliability of this unconventional staggered gate stack are investigated. At relatively low gate voltages, the gate current is suppressed owing to the buried-channel structure and the presence of GaON that presents an effective hole barrier. With more negative gate biases, the gate leakage was found to be dominated by the transport of holes that spillover from the p-channel through the SiN x via Poole-Frenkel emission. Based on this gate leakage mechanism at large gate bias, √ E model was used for gate lifetime prediction. The maximum applicable ON-state gate voltage of −7.3 V is obtained for a 10-year lifetime with a 1% gate failure rate. Index Terms-GaN, p-channel, SiN x /GaON gate stack, gate leakage, reliability. I. INTRODUCTIONG aN-BASED complementary logic (CL) circuits are actively pursued as energy-efficient on-chip peripheral modules for the further advancement of wide-bandgap semiconductor-based electronics [1], [2], [3]. Single-stage inverters with monolithically integrated n-and p-channel fieldeffect transistors (FETs) have been intermittently reported [4], [5], [6]. Recently, a complete set of elementary logic gates and multiple-stage logic circuits with desired "CMOSlike" characteristics have been demonstrated [7]. These results manifested the feasibility of constructing GaN CL circuits and also suggested GaN's power integration as an immediate beneficiary.

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Threshold Voltage Instability of Enhancement-Mode GaN Buried p-Channel MOSFETs

Cited by 21 publications

References 26 publications

Lattice-aligned gallium oxynitride nanolayer for GaN surface enhancement and function extension

Lattice-aligned gallium oxynitride nanolayer for GaN surface enhancement and function extension

GaN Non-Volatile Memory Based on Junction Barrier-Controlled Bipolar Charge Trapping

Gate Leakage and Reliability of GaN -Channel FET With SiNₓ/GaON Staggered Gate Stack

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