Threshold voltage in short channel polycrystalline silicon thin film transistors: Influence of drain induced barrier lowering and floating body effects

Abstract

The threshold voltage (VT) variations induced by the drain bias (Vds) are investigated in polycrystalline silicon thin film transistors (TFTs), with channel length ranging from 20 to 0.4 μm, by combining experimental measurements and two-dimensional (2D) numerical simulations. A careful analysis of the electrical characteristics in both subthreshold and off regime is performed, by taking in account also the effects of the leakage current field enhanced mechanisms on the overall generation-recombination rate. We show that the main causes of VT variations are the drain induced barrier lowering (DIBL) and floating body effects (FBEs), induced by impact ionization. The relative influence of FBEs and DIBL is analyzed by performing numerical simulations with or without including the impact ionization model. A detailed analysis of the 2D Poisson equation has allowed to identify and evaluate the contributions of DIBL and FBEs to the threshold voltage variation when both are present. It is found that, in short channel TFTs at high drain bias, the VT variations can’t be attributed to DIBL effect alone and there is a noticeable contribution of the FBEs to the threshold voltage reduction. From the numerical simulations, the influence of FBEs and DIBL on the electrostatic barrier at source junction and its reduction for increasing Vds is analyzed for long and short channel TFTs.

Edge Effects in Self-Heating-Related Instabilities in p-Channel Polycrystalline-Silicon Thin-Film Transistors

“…The p + source and drain regions were formed by B implant (a dose of 10 15 cm −2 ) through the oxide film, with the gate acting as a mask, and dopant activation was obtained by a second pass through the excimer laser. The effective channel length of the devices was 100 nm shorter than the nominal one L [7]. Fig.…”

“…Self-aligned p-channel polysilicon TFTs were fabricated, according to the process already reported in [7]. The 40-nmthick active layer was crystallized by excimer laser annealing, and the gate oxide, 60 nm thick, was deposited by PECVD at 300 • C using SiH 4 and N 2 O.…”

Lateral High-Voltage 4H-SiC MOSFETs

“…It is observed that V t is significantly decreased with higher V d for low-voltage devices, especially for channel length of 3 and 5μm. The DIBL effect which is defined as dV t /dV d is significant because the p-body is lightly doped in these devices [3]. On the other hand, the HV devices, even with L ch = 3 μm, do not show DIBL effect because most of the voltage drop is supported by RESURF region.…”

Anomalous drain‐induced barrier lowering effect of thin‐film transistors due to capacitive coupling voltage of light‐shield metal

“…In silicon‐on‐insulator structures like typical LTPS TFTs, the generated holes can be piled up, and this leads to inducing more a positive bias to the substrate. Consequently, V th decreases due to the high drain bias [5].…”