Threshold voltage extraction methods for MOS transistors

Dobrescu, Lidia; Petrov, Michail I.; Dobrescu, D.; Ravariu, Cristian

doi:10.1109/smicnd.2000.890257

Cited by 62 publications

(22 citation statements)

References 1 publication

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“…V th degradation has been inserted in V th0 transistor model parameter, used by the electrical simulator to compute the transistor threshold voltage. Empirical methods have been used to provide V th as a function of V th0 parameter to guarantee the correct degradation insertion [18,19]. A set of model cards have been created, each one representing a device with different V th .…”

Section: Simulation Resultsmentioning

confidence: 99%

BTI and HCI first-order aging estimation for early use in standard cell technology mapping

Butzen

Dal

Reis

et al. 2013

Microelectronics Reliability

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Section: Simulation Resultsmentioning

confidence: 99%

BTI and HCI first-order aging estimation for early use in standard cell technology mapping

Butzen

Dal

Reis

et al. 2013

Microelectronics Reliability

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“…the intercept with V GS axis from I DS /√g m,sat vs. V GS plot [16]) is less than 8% in worst-case compressive stress, and less than 1% for tensile stress (at 2.25 cm bending radii).…”

Section: B Effect Of Bending Axis Orientation Stress Typementioning

confidence: 91%

Out-of-Plane Strain Effects on Physically Flexible FinFET CMOS

Ghoneim

Alfaraj

Torres-Sevilla

et al. 2016

IEEE Trans. Electron Devices

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“…The CBCM technique has been extended to a fully differential approach and implemented by [23], [24], and [25]. We use the differential method in this thesis, and its design and implementation are explained in Section 3.2.1.…”

Section: Methods To Measure and Model Interconnectsmentioning

confidence: 99%

“…[23], [24], [25], integrated with switches so it can also be used with the scan chain approach, as illustrated in Figure 3-6 in Chapter 3.…”

Section: Measurement Methods Review and Adjustmentsmentioning

confidence: 99%

Study of CMOS Process Variation by Multiplexing Analog Characteristics

Gettings

Boning

2008

IEEE Trans. Semicond. Manufact.

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Aggressive technology scaling raises the need for efficient methods to characterize and model circuit variation at both the front and back end of line, where critical parameters such as threshold voltage and parasitic capacitance must be carefully modeled for accurate circuit performance. This thesis addresses this need by contributing a test circuit methodology for the extraction of spatial, layout and size dependent variations at both device and interconnect levels. The test chip uses a scan chain approach combined with low-leakage and low-variation switches, and Kelvin sensing connections, providing access to detailed analog device characteristics in large arrays of test devices. Front end of line (FEOL) test structures include transistors of different sizes, number of polysilicon fingers, polysilicon fingers proximity, and orientation, for both NMOS and PMOS MOSFETs. Back end of line (BEOL) test structures include parasitic coupling, plane to plane and crossover capacitances, measured using a charge-based capacitive measurement (CBCM) methodology integrated with switches in the scan chain.The testing of the designed test chip has proven successful for both device and interconnect test structures. Different layout practices in both NMOS and PMOS transistors are seen to result in significant differences in mean and standard deviation of measured output current, with 95% confidence or more. The FEOL structure analysis shows strong dependencies between layout practices: orientation offers a consistent but opposite offset in NMOS and PMOS transistors and variation increases for gate lengths split among fingers. Variation due to sizing follows Pelgrom's model, showing that variation increases for smaller gate lengths and widths, in both NMOS and PMOS transistors. Threshold voltage extraction and variation analysis also demonstrate how variation increases for smaller features. BEOL capacitances were extracted and subfemto Farad changes were detected for capacitive test structures. Spatial analysis reveals a large die-to-die trend in device performance. The parameter extraction and variation analyses made possible by the variation test chip enable the identification of likely variation sources, quantification of circuit impact and sensitivity, and specification of layout practices for variation minimization.

show abstract

Threshold voltage extraction methods for MOS transistors

Cited by 62 publications

References 1 publication

BTI and HCI first-order aging estimation for early use in standard cell technology mapping

BTI and HCI first-order aging estimation for early use in standard cell technology mapping

Out-of-Plane Strain Effects on Physically Flexible FinFET CMOS

Study of CMOS Process Variation by Multiplexing Analog Characteristics

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