Threshold voltage extraction in Tunnel FETs

Ortíz‐Conde, A.; Sánchez, F.J. Garcı́a; Muci, Juan; Sucre-González, Andrea; Martino, João Antônio; Agopian, Paula Ghedini Der; Claeys, Cor

doi:10.1016/j.sse.2013.12.010

Cited by 31 publications

(8 citation statements)

References 33 publications

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“…3(b). The distinct feature of the output characteristics in a TFET such as exponential onset and existence of drain threshold voltage (V th,d ) is evident [7], [14]. In general, a low V th,d is desirable in a TFET to reduce the transition time in CMOS-type TFET-based digital circuits [15], [37].…”

Section: Device Operation and Characteristicsmentioning

confidence: 99%

“…In general, TFETs exhibit exponential onset in the output characteristics because of the dependence of the BTBT on the gate-to-source voltage V GS and drain-to-source voltage V DS , in contrast to the conventional MOSFET [13], [14]. Therefore, in a TFET, there exist two types of threshold voltages: gate threshold voltage (V T H,G ) and drain threshold voltage (V T H,D ).…”

Section: Introductionmentioning

confidence: 99%

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Exploiting Within-Channel Tunneling in a Nanoscale Tunnel Field-Effect Transistor

Garg

Saurabh

2020

IEEE Open J. Nanotechnol.

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In this paper, using device simulations, we investigate electrical characteristics of a tunnel field-effect transistor (TFET) in which band-to-band tunneling (BTBT) occurs dominantly within the channel, rather than at source-channel junction. The within-channel BTBT is enabled by sharp bandbending induced by the dual material gate (DMG). The workfunctions of two metal gates are chosen, such that the surface potential profile exhibits a distinct step at the DMG interface. Consequently, even under equilibrium condition, a high lateral electric field and an abrupt tunneling junction exist at the DMG interface. When a small gate voltage is applied, the inherent lateral electric field aids in creating an abrupt band alignment and obtaining a small tunneling width. As a result, an excellent average subthreshold swing is obtained in the proposed device. We have also investigated scaling of channel lengths in the proposed device and have demonstrated that within-channel tunneling can be exploited for channel lengths of 40nm and above. Furthermore, low drain threshold voltage and suppressed drain-induced barrier lowering can be obtained in the proposed device. Moreover, in contrast to conventional TFETs, electrical characteristics of the proposed device are less susceptible to source doping variations and shift in gate-edge with respect to the source-channel junction. Index Terms-Tunnel field-effect transistor, dual material gate, subthreshold swing, threshold voltage, lateral electric field, process-induced variations.

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Section: Device Operation and Characteristicsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Exploiting Within-Channel Tunneling in a Nanoscale Tunnel Field-Effect Transistor

Garg

Saurabh

2020

IEEE Open J. Nanotechnol.

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“…For this reason, it is necessary to develop a consistent methodology that enables researchers in academia and industry to compare device performance between different architectures without being affected by the FoM extraction method. Moreover, there are several studies comparing the extraction method influence in some architectures like MOS-FETs [16] [18] [19], TFETs [20] or FinFETs [17], but there is work to be done both in recent devices like the GAA NW FET and in variability cases. In this work, we present a study using five different extraction techniques (SD, CC, LE, TD and TCR) to calculate the V TH values of a state-of-the-art variability-affected (GER, LER, MGG and RDD) GAA NW FET and assess the effect on the results.…”

Section: Introductionmentioning

confidence: 99%

Does the Threshold Voltage Extraction Method Affect Device Variability?

Espineira

García‐Loureiro

Seoane

2021

IEEE J. Electron Devices Soc.

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“…The ambipolarity in the device is the conduction for both high positive and high negative V gs while keeping the V DS only in one direction (negative for p-type devices and positive for n-type devices) (Cho et al 2011;Conde et al 2014;Hraziia et al 2012;Lee et al 2010;Shaker et al 2015). Ambipolarity can be reduced by using a HD structure, in which the gate dielectric is split into two regions; high-k dielectric near the source side and low-k dielectric near the drain side.…”

Section: Introductionmentioning

confidence: 99%