Threshold switching selector and 1S1R integration development for 3D cross-point STT-MRAM

Yang, Hongxin; Hao, Xinjun; Wang, Zihui; Malmhäll, R.; Gan, Huadong; Satoh, Kimihiro; Zhang, Jing; Jung, Dooyoung; Wang, Xiaobin; Zhou, Yuchen; Yen, B. Linju; Huai, Yiming

doi:10.1109/iedm.2017.8268513

Cited by 32 publications

(17 citation statements)

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“…The MOM diode MTJ stack employed in this design is similar to the experimentally validated device used in the 1S1R 3D cross-point STT-MRAM developed by avalanche [19][20][21]. However, employing the D-MTJ device in the SOT technology would be more efficient than in the STT technology as the energy and performance degradation effects of the diode would only exist in the read operation and is avoided in the write operation.…”

Section: Multi-bit Per Cell Dedicated Diode (Mbc-dd) Sot-mrammentioning

confidence: 99%

Area-Efficient Spin-Orbit Torque Magnetic Random-Access Memory

Ali¹

2020

Integrated Circuits/Microchips

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Spin-orbit torque magnetic random-access memory (SOT-MRAM) has shown promising potential to realize reliable, high-speed and energy-efficient on-chip memory. However, conventional SOT-MRAM requires two access transistors per cell. This limits the use of conventional SOT-MRAM in high-density memories. Thus, various architectures in the literature have been proposed to improve the area efficiency of the SOT-MRAM. In this chapter, these proposals are divided into two categories: non-diode-based SOT-MRAM and diode-based SOT-MRAM cells. The non-diode-based proposals may result in a 1-bit effective area saving up to 50% compared to the conventional SOT-MRAM, whereas the diode-based designs may result in 1-bit effective area-saving of up to 75%. However, the area saving may be accompanied by higher energy and reliability issue penalties. Therefore, here, the various proposals in the literature are presented, highlighting the pros and cons of each design. Moreover, the technology requirements to realize these proposals are discussed. Finally, the various designs are evaluated from both cell and system level perspectives.

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Section: Multi-bit Per Cell Dedicated Diode (Mbc-dd) Sot-mrammentioning

confidence: 99%

Area-Efficient Spin-Orbit Torque Magnetic Random-Access Memory

Ali¹

2020

Integrated Circuits/Microchips

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“…Read latency Write energy* Read energy* 30ns 10ns 4.5pJ/bit 0.7pJ/bit Table 1. STT-MRAM parameters used in the system [4][5] [6] *write/read energy includes energy of IO, peripheral and STT-MRAM array of last 3 layers of the network to the global buffer. Once we have the sum of gradients of weights and bias after processing a batch size of N, we need to update the weights as shown in a manner shown in Fig.…”

Section: Write Latencymentioning

confidence: 99%

Transfer and Online Reinforcement Learning in STT-MRAM Based Embedded Systems for Autonomous Drones

Yoon

Anwar

Rakshit

et al. 2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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In this paper we present an algorithm-hardware codesign for camera-based autonomous flight in small drones. We show that the large write-latency and write-energy for nonvolatile memory (NVM) based embedded systems makes them unsuitable for real-time reinforcement learning (RL). We address this by performing transfer learning (TL) on metaenvironments and RL on the last few layers of a deep convolutional network. While the NVM stores the meta-model from TL, an on-die SRAM stores the weights of the last few layers. Thus all the real-time updates via RL are carried out on the SRAM arrays. This provides us with a practical platform with comparable performance as end-to-end RL and 83.4% lower energy per image frame.

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“…Note that although the sneak paths are taken care of by using a simple diode, it cannot be used as a proxy for selector devices, which is in itself a research topic, and beyond the scope of this work. Many works on selector devices for MTJs can be found in the literature [43][44][45][46].…”

Section: (B) Magnetoelectric-magnetic Tunnel Junction Synaptic Crossbarmentioning

confidence: 99%

In situunsupervised learning using stochastic switching in magneto-electric magnetic tunnel junctions

Chakraborty

Agrawal

Jaiswal

et al. 2019

Phil. Trans. R. Soc. A.

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Threshold switching selector and 1S1R integration development for 3D cross-point STT-MRAM

Cited by 32 publications

References 0 publications

Area-Efficient Spin-Orbit Torque Magnetic Random-Access Memory

Area-Efficient Spin-Orbit Torque Magnetic Random-Access Memory

Transfer and Online Reinforcement Learning in STT-MRAM Based Embedded Systems for Autonomous Drones

In situunsupervised learning using stochastic switching in magneto-electric magnetic tunnel junctions

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