Three-valued logic in bounded model checking

Schuele, Tobias; Schneider, Klaus

doi:10.1109/memcod.2005.1487912

Cited by 6 publications

(7 citation statements)

References 42 publications

(48 reference statements)

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“…In our work we extended our former saturation-based bounded model checking approach to handle uncertainty about the specification, so it can produce three results: true, false, or ⊥ (where ⊥ denotes the unknown result). Three-valued logic [12,17] is a mathematical reasoning procedure for these three values, applied in many areas, including the analysis of asynchronous circuits, compilers, and model checking [3,16]. First we have to extend the logic, which can be seen in Table 1.…”

Section: Decision-making With Three-valued Logicmentioning

confidence: 99%

Bounded saturation-based CTL model checking

Vörös¹,

Darvas²,

Bartha³

2013

Proc. Estonian Acad. Sci.

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Abstract. Formal verification is becoming a fundamental step of safety-critical and model-based software development. As part of the verification process, model checking is one of the current advanced techniques to analyse the behaviour of a system. Symbolic model checking is an efficient approach to handling even complex models with huge state spaces. Saturation is a symbolic algorithm with a special iteration strategy, which is efficient for asynchronous models. Recent advances have resulted in many new kinds of saturation-based algorithms for state space generation and bounded state space generation and also for structural model checking. In this paper, we examine how the combination of two advanced model checking algorithms -bounded saturation and saturationbased structural model checking -can be used to verify systems. Our work is the first attempt to combine these approaches, and this way we are able to handle and examine complex or even infinite state systems. Our measurements show that we can exploit the efficiency of saturation in bounded model checking.

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Section: Decision-making With Three-valued Logicmentioning

confidence: 99%

Bounded saturation-based CTL model checking

Vörös¹,

Darvas²,

Bartha³

2013

Proc. Estonian Acad. Sci.

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“…of cache behaviour [1], and temporal properties of programs [19]. We show that threevalued logic is also a natural foundation to specify geometric problems.…”

Section: Fig 2 Truth Tables Of Three-valued Operatorsmentioning

confidence: 95%

“…Three-valued logic has proved to be an adequate tool in many areas of computer science [4,20,13,2,18,16,1,19]. We show that three-valued logic is well suited to define geometric primitives so that degenerate cases are consistently and concisely handled.…”

Section: Introductionmentioning

confidence: 94%

Dependable Polygon-Processing Algorithms for Safety-Critical Embedded Systems

Brandt

Schneider

2005

Embedded and Ubiquitous Computing – EUC 2005

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Abstract. Algorithms that process geometric objects become more and more important for many safety-critical embedded systems, e.g. for motion planning or collision detection, where correctness is indispensable. The main challenge to demonstrating correctness is the consistent handling of degenerate cases like collinear line segments. In this paper, we therefore propose the use of an interactive theorem prover to develop dependable geometry algorithms for safety-critical embedded systems. Our solution is based on the use of a three-valued logic to make degenerate cases explicit. Using the theorem prover, we are not only able to prove the correctness of the obtained algorithms, but also to directly derive a software library of provably correct geometry algorithms for safety-critical applications.

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“…Three-valued logic is often used in formal verification in order to create preserving abstractions, for example in bounded model-checking [19] or symbolic trajectory evaluation (STE) [11], [17]. A method for refining STE abstractions using SAT, auxiliary control variables and three-valued logic is described in [18].…”

Section: A Related Workmentioning

confidence: 99%

SAT-based synthesis of clock gating functions using 3-valued abstraction

Arbel

Rokhlenko

Yorav

2009

2009 Formal Methods in Computer-Aided Design

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Clock gating is a power reduction technique for digital circuits that works by eliminating unnecessary switching of parts of the clock network, a power-hungry component in hardware designs. An effective approach to clock gating synthesis is based on a functional analysis of the design using BDDs. Algorithms of this type attempt to build a BDD for a clock gating circuit and then reduce its size with an approximation. If the BDD of a particular latch grows too large the attempt to gate that latch is aborted.We replace BDDs with a SAT-based technique combined with 3-valued abstraction. Our technique generates the approximation directly from the circuit, and thus avoids the explosion. Furthermore, our technique is incremental in the sense that it produces a partial result (a weaker approximation) if time or memory limits are exceeded. Our experimentation shows that more than 70% of latches that could not be gated using the BDD-based approach were gated by the SAT-based method.

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Three-valued logic in bounded model checking

Cited by 6 publications

References 42 publications

Bounded saturation-based CTL model checking

Bounded saturation-based CTL model checking

Dependable Polygon-Processing Algorithms for Safety-Critical Embedded Systems

SAT-based synthesis of clock gating functions using 3-valued abstraction

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