Three-level Gate Drive Technique for Enhancing Switching Loss Reduction in Triple-Gate IGBTs

Sakano, Tatsunori; Adachi, Kento; Inokuchi, T.; Takao, Kazuto; Iwakaji, Yoko; Gejo, Ryohei; Matsudai, Tomoko

doi:10.1109/ispsd49238.2022.9813666

Cited by 2 publications

(2 citation statements)

References 3 publications

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“…By modulating the carrier distribution in the on-state, IEGT, PNM-IGBT, and CSTBT reduce the V on signi cantly. Additionally, adjusting the gate structure to reduce gate charge or optimizing the gate control strategy have led to a noteworthy reduction in switching losses of these devices[8], [9], [10], [11], [12], [13], [14].…”

Section: Introductionmentioning

confidence: 99%

A novel Self-Biased pMOS Clamped Deep Trench CSTBT with Enhanced Short-Circuit Capability

Guo,

Qian,

Chen

et al. 2024

Preprint

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In this work, a novel deep trench CSTBT (DT-CSTBT) features emitter trench and the P-layer is proposed and investigated by simulation. The self-biased pMOS, comprising an emitter trench, N-CS layer, P-layer, and P-well, demonstrates an excellent clamping effect potential. The proposed DT-CSTBT suppresses the saturation current under the clamping effect, resulting in a 23.5% expansion of the short-circuit safe operating area (SCSOA). It ensures the better reliability of the gate due to the high electric field away from the gate. Furthermore, the tradeoff relationship between on-state voltage (Von) and turn-off loss (Eoff) of the new structure is also improved by 23.2% compared with the conventional CSTBT.

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Section: Introductionmentioning

confidence: 99%

A novel Self-Biased pMOS Clamped Deep Trench CSTBT with Enhanced Short-Circuit Capability

Guo,

Qian,

Chen

et al. 2024

Preprint

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“…Dual-gate IGBTs, [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30] which have two independent control gates, can further reduce E off by suppressing the stored carrier density in the n− drift region prior to the turn-off switching. We proposed an integrated time and space carrier controllable dual-gate HiGT (i-TASC 31) ) that has two different hole injection efficiency regions within one chip and demonstrated that the trade-off between V CEsat and E off can be greatly improved.…”

Section: Introductionmentioning

confidence: 99%

Structural parameter analysis on 6.5 kV integrated time and space carrier controllable dual-gate HiGT (i-TASC)

Suzuki

Miyoshi

Moritsuka

et al. 2023

Jpn. J. Appl. Phys.

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A dual-gate insulated gate bipolar transistor (IGBT), which achieves low loss through dynamic gate control, is a remarkable technology. However, the influence of device structures on switching loss has not been analyzed in detail.In this paper, we clarify the optimal structure in terms of turn-off loss (E off) reduction for a proposed dual-gate IGBT (i-TASC) that can dynamically control the stored carriers with one-chip fabrication.A boundary region (TS) is introduced in the i-TASC and the conductivity modulation before the turn-off can be sufficiently suppressed by securing the width of TS. A prototyped 6.5 kV i-TASC demonstrates 45 % lower E off compared with the conventional single-gate IGBTs.

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Three-level Gate Drive Technique for Enhancing Switching Loss Reduction in Triple-Gate IGBTs

Cited by 2 publications

References 3 publications

A novel Self-Biased pMOS Clamped Deep Trench CSTBT with Enhanced Short-Circuit Capability

A novel Self-Biased pMOS Clamped Deep Trench CSTBT with Enhanced Short-Circuit Capability

Structural parameter analysis on 6.5 kV integrated time and space carrier controllable dual-gate HiGT (i-TASC)

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