Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs

Lü, Pei; Yang, Can; Li, Yifei; Li, Bo; Han, Zhengzhi

doi:10.3390/eng2040039

Cited by 10 publications

(7 citation statements)

References 38 publications

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“…Currently, the impact of radiation on semiconductors has a tradeoff relationship between the SEE and the TID effect, and recently, based on simulations, research has been actively conducted on tolerance technologies of these two effects for advanced transistors in nanoscale process [12], [20]. This article proposed a technology that can simultaneously ensure resistance to two types of radiation effects in a submicrometer process that can be fabricated on a chip and verified its feasibility.…”

Section: Discussionmentioning

confidence: 99%

Complex Design of CMOS Logic With Tolerance to Particle and Cumulative Radiation

Lee

2024

IEEE Trans. Electron Devices

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Silicon-based electronic components exposed to the radiation environment experience transient and cumulative damage, which causes performance degradation, malfunction, and burnout of the entire electronic system. In this study, the silicon-on-insulator (SOI) process technology was applied to enhance the single event effect (SEE) tolerance of bulk complementary metal-oxidesemiconductor (CMOS)-based logic circuits, which are vulnerable to space particle radiation. SOI CMOS processes are susceptible to total ionizing dose (TID) effects because of an additional oxide layer. A layout-modification technique (LMT) was proposed to overcome this problem. The SEE tolerance characteristics of the SOI process logic were verified in advance using radiation response modeling and simulation. The proposed radiation-hardened (RH) SOI CMOS logic was designed and implemented on a chip using a 0.5-µm CMOS test process. Radiation tests were conducted on the proposed logic chip to validate its SEE resistance to 50-and 25-MeV proton particles and its tolerance to TID effects for a total dose of 15-kGy(Si) gamma rays. The proposed SOI CMOS logic with the LMT can mitigate the atypical effects caused by radiation particles in semiconductor devices in radiation environments, such as space and nuclear power plants, thereby ensuring sufficient survival time under cumulative effects.

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Section: Discussionmentioning

confidence: 99%

Complex Design of CMOS Logic With Tolerance to Particle and Cumulative Radiation

Lee

2024

IEEE Trans. Electron Devices

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“…The minimum delta (δ) in Equation ( 3) can be used to determine the chosen parameters without considering kink effects, which are listed in Table 1 [8]. In the table, the minimum delta at different gate biases requires different k n , lambda (λ), and threshold voltages.…”

Section: Applicationmentioning

confidence: 99%

“…Therefore, current-versus-voltage characteristic curves showing the electrical performances of transistors are necessarily parameter-extracted in the model. Nevertheless, researchers are still intrigued to know if the "modified" conventional formula is applicable for fitting repeated characteristic curves [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. Useful parameters are supposed to be constants in the model, even though they need interpreting.…”

Section: Introductionmentioning

confidence: 99%

Conclusive Model-Fit Current–Voltage Characteristic Curves with Kink Effects

Yang,

Chi

2023

Applied Sciences

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Current–voltage characteristic curves of NFinFET are presented and fitted with modified current–voltage (I-V) formulas, where the modified term in the triode region is demonstrated to be indispensable. In the as-known I-V formula, important parameters need to be determined to make both the measured data and the fitting data as close as possible. These parameters include kN (associated with the sizes of the transistor and mobility), λ (associated with early voltage), and Vth (the threshold voltage). The differences between the measured data and the fitting data vary with the applied source–drain bias, proving that the mobility of the carriers is not consistently constant. On the other hand, a modified formula, called the kink effect factor, is negatively or positively added, simulating solitary heat waves or lattice vibration, which disturb the propagation of carriers and thus influence the source–drain current (IDS). The new statistical standard deviations (δ) are then found to be effectively suppressed as the kink effect is taken into account.

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“…The achievable function of the process is mostly due to the good conformality (step coverage) of chemical vapor deposition, in which SiH4 (silane) is controlled at a chosen flow rate and the ambient is sustained at an appropriate temperature and at certain pressure to achieve a good deposition rate in kinetic regime. [7][8][9][10][11][12][13][14][15] Somehow, the electrical performances of transistors are mainly manifested in current-versusvoltage characteristic curves. Those curves are necessarily parameter-extracted in the model, which is useful to develop circuit design.…”

Section: Introductionmentioning

confidence: 99%

Conclusive Algorithm with Kink Effects for Fitting 3-D FinFET and Planar MOSFET Characteristic Curves

Yang,

Chi,

Yang

et al. 2024

Preprint

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NFinFET transistors with fin channel length 90nm and a planar MOSFET transistor with channel length 180nm and 90nm are presented with characteristic curves at various gate biases. A finalized algorithm with kink effects is effectively responsible for addressing the field effect transistors. The algorithm includes the modified conventional current-voltage formula and a nonlinear heat-associated kink solution which is simplified as a Gaussian form. Three parameters in modified model includes kN (related with channel width, channel length, and gate oxide capacitor, and proportional to the mobility of carriers)Vth(Threshold Voltage), and (the inverse of Early Voltage). Those parameters are determined to minimize the discrepancies between the measured data and the fitting values, but leave kinks located at around (VGS－Vth), which are deliberately eliminated by the Gaussian form because of the agitation of thermal kink effects. The whole fitting is made to be as close as the as-measured IDS-VDS. In the mean time, those determined parameters are physically meaningful after the analysis has been done.

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Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs

Cited by 10 publications

References 38 publications

Complex Design of CMOS Logic With Tolerance to Particle and Cumulative Radiation

Complex Design of CMOS Logic With Tolerance to Particle and Cumulative Radiation

Conclusive Model-Fit Current–Voltage Characteristic Curves with Kink Effects

Conclusive Algorithm with Kink Effects for Fitting 3-D FinFET and Planar MOSFET Characteristic Curves

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