Three-dimensional structure recognition of circuit patterns on semiconductor devices using multiple SEM images detected in different electron scattering angles

Yasui, Kanji; Osaki, Mayuka; Miyamoto, Atsushi; Namai, Hitoshi

doi:10.1016/j.microrel.2020.113628

Cited by 3 publications

(2 citation statements)

References 12 publications

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“…The accurate measurement of the line width is a crucial task for process development and control as the line feature continues to shrink. The commonly used line width measurement technologies include atomic force microscopy (AFM), scanning electron microscopy (SEM), and transmission electron microscopy (TEM) [3][4][5][6][7][8] . The three-dimensional line width AFM image is the convolution result between the actual surface topography and the tip geometry used during scanning [9][10][11][12] .…”

Section: Introductionmentioning

confidence: 99%

Development and characterization of nano line width based on the fusion of high-resolution transmission electron microscopy and scanning electron microscopy

Shi,

Wang,

Zhang

et al. 2024

Preprint

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The nano line width is the critical dimension of integrated circuits. With the continuous reduction of key technology nodes, integrated circuits have created higher requirements for line width reference materials and their accurate measurement. We developed 7 nm, 22 nm, and 45 nm line width reference materials based on the multilayer deposition technique. Their line features were characterized according to the proposed fusion method. This method combines the advantages of both high-resolution transmission electron microscopy (HRTEM) and scanning electron microscopy (SEM), not only reducing the influence of boundary effects on the accuracy of line width measurement in SEM, but also disseminating the destructive HRTEM results. Moreover, the measurement results trace to the International System of Units (SI) meter definition using the silicon lattice constant built-in the line width. Experimental results illustrated that the measurement accuracy of the proposed method was improved by 40% compared with SEM alone, which meets the accuracy requirements for line width measurement in integrated circuits.

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Section: Introductionmentioning

confidence: 99%

Development and characterization of nano line width based on the fusion of high-resolution transmission electron microscopy and scanning electron microscopy

Shi,

Wang,

Zhang

et al. 2024

Preprint

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“…On the contrary, because of the high integration of semiconductor circuit patterns, the line width of circuits is becoming smaller [10]. The temperature of ESC in the 20 ~ 30 nm line-width etching process is room temperature, but the −20°C temperature level is primarily used at the 10 nm level.…”

Section: Introductionmentioning

confidence: 99%

Perspective Chapter: Ultra-Low Temperature Chillers for Semiconductor Manufacturing Process

Yoon¹,

Son²,

Seol³

et al. 2023

Latest Research on Energy Recovery

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The growth of the semiconductor market and advancement of manufacturing technology have led to an increase in wafer size and highly integrated semiconductor devices. The temperature of the supplied cooling medium from the chiller that removes the heat produced in the semiconductor manufacturing process is required to be at a lower level because of the high integration. The Joule-Thomson cooling cycle, which uses a mixed refrigerant (MR) to produce the cooling medium at a level of −100°C required for the semiconductor process, has recently gained attention. When a MR is used, the chiller’s performance is heavily influenced by the composition and proportions of the refrigerant charged to the chiller system. Therefore, this paper introduces a cooling cycle that uses an MR to achieve the required low temperature of −100°C in the semiconductor manufacturing process and provides the results of simple experiments to determine the effects of different MR compositions.

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Characteristic Analysis and Category Recognition of Insulating Paperboard Surface Pattern Based on Image Morphology Calculation

Luo,

Zhang,

Fang

et al. 2023

2023 IEEE/IAS Industrial and Commercial Power System Asia (I&CPS Asia)

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Three-dimensional structure recognition of circuit patterns on semiconductor devices using multiple SEM images detected in different electron scattering angles

Cited by 3 publications

References 12 publications

Development and characterization of nano line width based on the fusion of high-resolution transmission electron microscopy and scanning electron microscopy

Development and characterization of nano line width based on the fusion of high-resolution transmission electron microscopy and scanning electron microscopy

Perspective Chapter: Ultra-Low Temperature Chillers for Semiconductor Manufacturing Process

Characteristic Analysis and Category Recognition of Insulating Paperboard Surface Pattern Based on Image Morphology Calculation

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