Three-dimensional routing for multilayer ceramic printed circuit boards

Hanafusa, Akihiko; Yamashita, Yoshimi; Yasuda, Makoto

doi:10.1109/iccad.1990.129932

Cited by 23 publications

(6 citation statements)

References 3 publications

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“…Three-dimensional maze routing is a common technique [9]. However, it suffers from large memory requirements since the entire three dimensional grid Manuscript must be stored, and it is very sensitive to the ordering of the nets.…”

Section: Introductionmentioning

confidence: 99%

The MCG autorouter for multichip modules

Carothers

Li²

1999

IEEE Trans. Circuits Syst. I

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A multilayer, multichip module (MCM) router, called MCG, is introduced for x-y routing. An efficient method has been derived to allow candidate routes for the nets to be considered simultaneously for compatibility, rather than incrementally extending routes or routing one net at a time, as in many other techniques, and thus allowing incorporation of accurate models for determining the potential for crosstalk and delay problems during the routing process. In comparisons with other routers on industrial benchmarks, the MCG router has shown substantial improvement in routing density, number of layers, number of vias, and total interconnect length over routers such as V4R and SLICE. Our test results show up to 18% improvement in via count and up to 33% improvement in the required number of routing layers for these examples over V4R. One of the benchmarks presented contains 37 VHSIC gate arrays, over 7000 nets, and over 14 000 pins (pads).

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Section: Introductionmentioning

confidence: 99%

The MCG autorouter for multichip modules

Carothers

Li²

1999

IEEE Trans. Circuits Syst. I

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“…For example, the MCM developed for the IBM 3081 mainframe has 33 layers of molybdenum conductors (including 1 bonding layer, 5 distribution layers, 16 interconnection layers, 8 voltage reference layers, and 3 power distribution layers [2,3]). Fujitsu's latest supercomputer, the VP-2000, uses ceramic PCBs with over 50 interconnection layers [12]. However, the routing model for MCMs and PCBs is different from the routing model for ICs, because in MCM and PCB designs the routing space is no longer decomposed into channels and switchboxes.…”

Section: Introductionmentioning

confidence: 99%

A provably good multilayer topological planar routing algorithm in IC layout designs

Cong¹,

Hossain

Sherwani

1993

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Given a number of routing layers, the multilayer topological planar routing problem is to choose a maximum (weighted) set of nets so that each net in the set can be topologically routed entirely in one of the given layers without crossing other nets. This problem has important application in the layout design of multilayer IC technology, which has become available recently. In this paper, we present a provably good approximation algorithm for the multilayer topological planar routing problem. Our algorithm, called the iterative-peeling algorithm, finds a solution whose weight is guaranteed to be at least 1 − e 1 ∼ ∼ 63.2% of the weight of an optimal solution. The algorithm works for multi-terminal nets and arbitrary number of routing layers. For fixed number of routing layers, we have even tighter performance bounds. In particular, the performance-ratio of the iterative-peeling algorithm is at least 75% for two layer routing, and is at least 70.4% for three layer routing. Experimental results confirm that our algorithm can always route majority of the nets without using vias even when the number of routing layers is fairly small.

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“…This is the total number of routes, and can be simplified as (1) Among the terms of (1), can be simplified to: . We can substitute it to (1), and simplify to (2) We now show that the last summation term of (2) can be reduced.…”

Section: Density Estimationmentioning

confidence: 99%

“…Under the current technology, application-specific integerated circuit (ASIC) designs are frequently implemented with four to six layers of metals [10]. Most printed circuit boards (PCBs) and multichip modules (MCMs) use multiple layers where their logic cells occupy the bottom layers and their interconnects are routed in upper metal layers [2], [10]. Three-dimensional (3-D) layouts [2], [5], [8], [12], [13] and placement [3] were considered for VLSI.…”

mentioning

confidence: 99%

“…Most printed circuit boards (PCBs) and multichip modules (MCMs) use multiple layers where their logic cells occupy the bottom layers and their interconnects are routed in upper metal layers [2], [10]. Three-dimensional (3-D) layouts [2], [5], [8], [12], [13] and placement [3] were considered for VLSI. Three-dimensional architectures have also been proposed for field-programmable gate arrays (FPGAs) [7], [9] and reconfigurable computing [1].…”

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confidence: 99%

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Congestion Estimation for 3-D Circuit Architectures

Cheng

Hung

Yang

et al. 2004

IEEE Trans. Circuits Syst. II

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Abstract-Three-dimensional (3-D) routing is an important step in deep submicrometer very large-scale integrated design. Given a 3-D grid graph and a set of two-terminal nets to be routed, we propose a probabilistic model to calculate the routing density (congestion) on each edge of the grid graph. The routing density provides a direct congestion estimation. Our experimental results demonstrate the effectiveness of the method on routing benchmarks.

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Three-dimensional routing for multilayer ceramic printed circuit boards

Cited by 23 publications

References 3 publications

The MCG autorouter for multichip modules

The MCG autorouter for multichip modules

A provably good multilayer topological planar routing algorithm in IC layout designs

Congestion Estimation for 3-D Circuit Architectures

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