Three-dimensional numerical simulation of single event upset effect based on 55 nm DICE latch unit

Abstract

With the development of nanoscale circuit technology, the on-track error rate of digital circuits and the impact of single event upset has become more pronounced. The radiation resistance research on DICE SRAM or DICE flip-flop devices has been carried out by scholars from domestic and foreign, including 65 nm, 90 nm, and 130 nm, etc. However, scholars have never published any related articles about the 55 nm DICE latch. With the three-dimensional device model of the 55 nm bulk silicon process established by the simulation tool TCAD, we verified the reinforcement performance of the DICE circuit, and clarified the effects of different incident conditions on DICE circuits. At the same time, we compared the anti-SEU performance of NMOS and PMOS transistors in the 55 nm process through comparative simulation experiments and quantitative analysis. The investigation shows that one of the important factors is the LET value which affecting the generation rate of electron-hole pairs. A higher LET value will extend the upset recovery time of devices and increase the peak of voltage. In addition, the difference in the charge-sharing mechanism of transistors leads to the recovery time of PMOS higher than NMOS; As the angle of incidence increases, the charge-sharing mechanism between adjacent devices are enhanced, and electron-hole pairs ionized in sensitive regions increased. Due to the difference in charge mobility, the sensitivity of the angle of incidence of Nhit in DICE is much greater than that of Phit. Therefore, strict tilt angle incident test evaluation is required for DICE devices before practical application; Finally, the large distance between adjacent MOS tubes will weaken the charge-sharing mechanism and reduce the charge collection of adjacent MOS tubes, it’s found that the distance between the MOS transistors in the 55 nm process must not be less than 1.2 μm by device simulation. Relevant simulation results can provide a theoretical basis and data support for the study of the physical mechanism of SEU and reinforcement technology, then accelerate the application of memory devices in the aerospace field.