Threading dislocations in GaN high-voltage switches

Setera, Brett; Christou, A.

doi:10.1016/j.microrel.2021.114336

Cited by 13 publications

(5 citation statements)

References 94 publications

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“…This saturation is attributed to either the degradation of crystal quality or self-compensation of the C. 21,22) Threading screw dislocations (TSDs) contribute to increased electrical leakage, while edge dislocations affect carrier scattering and charge trapping. 23,24) In our study, we suggest that the substantial presence of TSDs in sample E leads to significant leakage at low voltages. However, voltage application continues, the gradual charging of C-related defects may alleviate the leakage resulting from TSD.…”

Section: Resultsmentioning

confidence: 51%

Alleviation of the on-state dynamic conductance decline in a GaN high electron mobility transistor with heavy carbon doping

Zhang,

Wu,

Luo

et al. 2024

Jpn. J. Appl. Phys.

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Carbon doping is a standard blocking-voltage-enhancing technique for commercial silicon substrate-based AlGaN/GaN power switching transistors, although the incorporation of carbon into GaN may deteriorate the dynamic on-state resistance (dy-R on) properties of the device. Commonly, researchers have believed that the greater the carbon doping, the greater the deterioration in dy-R on. Surprisingly, in this work, the opposite was observed: the dy-R on value decreased as the carbon concentration increased, particularly when the density exceeded several 1017 cm−3. This phenomenon is explained by the effect of electric field-induced band-to-band electron tunneling into the two-dimensional electron gas (2DEG) conduction channel, originating from the ionization of acceptor-like nitrogen site carbon atoms (CN) in the device off-state with large drain bias. Simulation data indicated that negatively ionized CN may generate a much larger electric field in samples with higher carbon doping, which may induce a narrower 2DEG back energy band barrier that increases the possibility of electron band-to-band tunneling.

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Section: Resultsmentioning

confidence: 51%

Alleviation of the on-state dynamic conductance decline in a GaN high electron mobility transistor with heavy carbon doping

Zhang,

Wu,

Luo

et al. 2024

Jpn. J. Appl. Phys.

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“…Відповідно пошук причин та методів уникнення описаного виду систематичного браку являється актуальним науково-технічним завданням. Так, в [2,3] розглянуто проблему дефектоутворення в структурах на основі GaN для силової електроніки, та впливу порушень структури кристалічної гратки на продуктивність і безвідмовність при високих напругах живлення. У [4,5] представлено вплив дефектів кристалічної структури кремнію на механізм генерації напруги пробою в низьковольтних силових MOSFET, що працюють у лавинному режимі.…”

Section: вступunclassified

Technological Causes of p-n-Junction Break-down of Silicon p-i-n Photodiodes

Kukurudziak¹

2022

Microsyst., Electron. & Acoust.

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During the manufacture of coordinate quadrant p-i-n photodiodes with a high reverse bias voltage Ubias≥200 V, it was observed the presence of a systematic lack of products at the level of the dark current of one (rarely several) photosensitive element. After measuring the volt-ampere characteristics, it was seen that the cause of this is a breakdown of the p-n junction. Effective methods of increasing the breakdown voltage are reducing the specific resistance of the silicon used, increasing the thickness of the substrate and the depth of the p-n junctions, reducing the concentration of alloying impurities, but these methods should be used in cases that allow the degradation of the relevant parameters to be neglected. In particular, it is necessary to provide a level of technology that reduces the probability of a breakdown. A number of technological factors that can be the reasons for reducing the breakdown voltage of the p-n junction have been established and investigated. Strong influence on the breakdown voltage. have crystallographic defects, in particular dislocations falling into the region of the p-n junction. By reducing the concentration of alloying impurities, it is possible to significantly reduce the density of dislocations with a small increase in the levels of dark currents. This helps to eliminate the probability of a breakdown. After operations of sprinkling chrome-gold on the reverse side of such a substrate, the appearance of breakdowns was detected. The cause of which are defects formed as a result of local melting of silicon when gold "droplets" with a temperature higher than the melting temperature of silicon fall on it, as a result of boiling in the evaporator. Іt is possible to reduce the probability of the appearance of these defects by spraying from closed evaporators or by increasing the etchability of spraying on the damper. During photolithography, in particular, when etching windows in the oxide, etching wedges are formed, which direct the output of the p-n junction to the surface at an acute angle. These areas are places with an increased level of electric field intensity, respectively, places of probable localization of the breakdown. This can be avoided by using photoresists that provide minimal etching wedges. Irregularities between the oxide windows can also lead to a decrease in the probo voltage, the probability of this can be reduced by careful control of the development and exposure operations and the use of defect-free templates. Another reason for a breakdown can be a violation of the p-n junction due to welding of the contact terminals. In this case, it is a thermal breakdown. This can be avoided by increasing the size of the contact pads with their expansion on silicon oxide, accordingly, welding on the surface of the oxide reduces the probability of a hole. Another method is a local increase in the depth of the p-n junction, but in this case additional technological operations must be carried out.

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“…In addition, the TDD in the GaN layer is still high, impeding the performance of vertical GaN‐on‐Si power devices. [ 27 ] It is thus essential to further increase the thickness and reduce the TDD in GaN layers on Si.…”

Section: Introductionmentioning

confidence: 99%

Terrace Engineering of the Buffer Layer: Laying the Foundation of Thick GaN Drift Layer on Si Substrates

Chen

Zhang

Liu

et al. 2023

Adv Elect Materials

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Vertical GaN-on-Si devices are promising for the next-generation high-voltage power electronics with low cost and high efficiency. However, their applications are impeded by the limited thickness of crack-free GaN layers and high threading dislocation density (TDD) in the layer. Buffer layers are crucial for stress control while they usually behave with poor surface morphology, which causes early stress relaxation in GaN and limited thickness. Hereby, a terrace engineering approach for the buffer layers is proposed. Through tuning the supersaturation ratio, the terrace width can be manipulated and an atomically smooth AlGaN buffer layer can be realized, which effectively reduces the compressive stress relaxation and provides a firm foundation for thick GaN growth. As a result, a 7.5 μm thick GaN drift layer with TDD as low as 8.6 × 10 7 cm −2 is achieved on Si substrates. The room temperature electron mobility of the GaN drift layer can be raised up to 1210 cm 2 V −1 s −1 . The fabricated PiN diode shows a high breakdown voltage of 1058 V as well as a high on/off ratio of 10 12 . This work thus truly demonstrates the potential of high-performance and low-cost GaN-based electronic as well as optoelectronic devices on Si platforms.

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Threading dislocations in GaN high-voltage switches

Cited by 13 publications

References 94 publications

Alleviation of the on-state dynamic conductance decline in a GaN high electron mobility transistor with heavy carbon doping

Alleviation of the on-state dynamic conductance decline in a GaN high electron mobility transistor with heavy carbon doping

Technological Causes of p-n-Junction Break-down of Silicon p-i-n Photodiodes

Terrace Engineering of the Buffer Layer: Laying the Foundation of Thick GaN Drift Layer on Si Substrates

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