Thread-Level Speculation on a CMP can be energy efficient

Renau, Jose; Strauß, Karin; Ceze, Luís; Liu, Wei; Sarangi, Smruti R.; Tuck, James; Torrellas, Josep

doi:10.1145/1088149.1088178

Cited by 85 publications

(102 citation statements)

References 26 publications

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“…Much prior work has investigated thread-level speculation (TLS) schemes to parallelize sequential programs [25,28,60,61,66,69]. TLS schemes ship tasks from function calls or loop iterations to different cores, run them speculatively, and commit them in program order.…”

Section: Background On Hw Support For Speculative Parallelismmentioning

confidence: 99%

“…By contrast, most TLS systems use lazy versioning (buffering speculative data in caches) or more expensive multiversioning [11,25,28,29,56,60,61,66,68,69] to limit the cost of aborts. Some early TLS schemes are eager [25,80], and they still suffer from the limitations discussed in Sec.…”

Section: Speculative Execution and Versioningmentioning

confidence: 99%

“…Moreover, many of these algorithms rarely have true data dependences among tasks, and their maximum achievable parallelism exceeds 100×. It may seem that thread-level speculation (TLS) [28,60,66,68], which speculatively parallelizes sequential programs, could exploit this parallelism. However, this is not the case due to two reasons (Sec.…”

Section: Introductionmentioning

confidence: 99%

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A scalable architecture for ordered parallelism

Jeffrey¹,

Subramanian²,

Yan³

et al. 2015

Proceedings of the 48th International Symposium on Microarchitecture

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We present Swarm, a novel architecture that exploits ordered irregular parallelism, which is abundant but hard to mine with current software and hardware techniques. In this architecture, programs consist of short tasks with programmer-specified timestamps. Swarm executes tasks speculatively and out of order, and efficiently speculates thousands of tasks ahead of the earliest active task to uncover ordered parallelism. Swarm builds on prior TLS and HTM schemes, and contributes several new techniques that allow it to scale to large core counts and speculation windows, including a new execution model, speculation-aware hardware task management, selective aborts, and scalable ordered commits.We evaluate Swarm on graph analytics, simulation, and database benchmarks. At 64 cores, Swarm achieves 51-122× speedups over a single-core system, and outperforms software-only parallel algorithms by 3-18×.

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Section: Background On Hw Support For Speculative Parallelismmentioning

confidence: 99%

Section: Speculative Execution and Versioningmentioning

confidence: 99%

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A scalable architecture for ordered parallelism

Jeffrey¹,

Subramanian²,

Yan³

et al. 2015

Proceedings of the 48th International Symposium on Microarchitecture

View full text Add to dashboard Cite

show abstract

“…Our evaluation is conducted using a modified version of the SESC [24] execution-driven simulator. The simulator models an out-of-order superscalar microprocessor in a detailed manner and fully executes "wrong-path" instructions.…”

Section: A Methodologymentioning

confidence: 99%

Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors

Subramanyan

Singh

Saluja

et al. 2011

2011 IEEE 29th International Conference on Computer Design (ICCD)

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“…Table 1 provides a classification of the proposed simulation frameworks mainly focused on the DVFS/DFS support, GALS design capabilities and availability of PLL models. The SESC simulator [31] provides cycle-accurate simulation of bus-based multi-core processors, based on the MIPS architecture. However, it does not support Network-on-Chip architectures as well as neither DVFS nor asynchronous NoC design.…”

Section: Simulation Frameworkmentioning

confidence: 99%

A control-based methodology for power-performance optimization in NoCs exploiting DVFS

Zoni

Terraneo

Fornaciari

2015

Journal of Systems Architecture

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a b s t r a c tNetworks-on-Chip (NoCs) are considered a viable solution to fully exploit the computational power of multi-and many-cores, but their non negligible power consumption requires ad hoc power-performance design methodologies. In this perspective, several proposals exploited the possibility to dynamically tune voltage and frequency for the interconnect, taking steps from traditional CPU-based power management solutions. However, the impact of the actuators, i.e. the limited range of frequencies for a PLL (Phase Locked Loop) or the time to increase voltage and frequency for a Dynamic Voltage and Frequency Scaling (DVFS) modules, are often not carefully accounted for, thus overestimating the benefits. This paper presents a control-based methodology for the NoC power-performance optimization exploiting the Dynamic Frequency Scaling (DFS). Both timing and power overheads of the actuators are considered, thanks to an ad hoc simulation framework. Moreover the proposed methodology eventually allows for user and/or OS interactions to change between different high level power-performance modes, i.e. to trigger performance oriented or power saving system behaviors. Experimental validation considered a 16-core architecture comparing our proposal with different settings of threshold-based policies. We achieved a speedup up to 3 for the timing and a reduction up to 33.17% of the power ⁄ time product against the best threshold-based policy. Moreover, our best control-based scheme provides an averaged power-performance product improvement of 16.50% and 34.79% against the best and the second considered threshold-based policy setting.

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Thread-Level Speculation on a CMP can be energy efficient

Cited by 85 publications

References 26 publications

A scalable architecture for ordered parallelism

A scalable architecture for ordered parallelism

Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors

A control-based methodology for power-performance optimization in NoCs exploiting DVFS

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