Thin-film transistors in polycrystalline silicon by blanket and local source/drain hydrogen plasma-seeded crystallization

Abstract

Thin film n-channel transistors have been fabricated in polycrystalline silicon films crystallized using hydrogen plasma seeding, by using several processing techniques with 600 to 625 C or 1000 C as the maximum process temperature. The TFT's from hydrogen plasma-treated films with a maximum process temperature of 600 C, have a linear field-effect mobility of 35 cm 2 /Vs and an ON/OFF current ratio of 10 6 , and TFT's with a maximum process temperature of 1000 C, have a linear field-effect mobility of 100 cm 2 /Vs and an ON/OFF current ratio of 10 7. A hydrogen plasma has also then been applied selectively in the source and drain regions to seed large crystal grains in the channel. Transistors made with this method with maximum temperature of 600 C showed a nearly twofold improvement in mobility (72 versus 37 cm 2 /Vs) over the unseeded devices at short channel lengths. The dominant factor in determining the field-effect mobility in all cases was the grain size of the polycrystalline silicon, and not the gate oxide growth/deposition conditions. Significant increases in mobility are observed when the grain size is in order of the channel length. However, the gate oxide plays an important role in determining the subthreshold slope and the leakage current.

Complementary metal-oxide-semiconductor thin-film transistor circuits from a high-temperature polycrystalline silicon process on steel foil substrates

“…The TFTs with channel lengths m shows substantially better performance than the TFTs with longer channels, in particular the n-channel devices. This result suggests that the grain size in 750 C 2 min polysilicon may be as large as 2 m, or that 1-h long post ion-implantation hydrogenation was not long enough for TFTs with channels 2 m. The earlier results on TFTs fabricated on silicon wafer substrates with channel length ranging from 2 m to 14 m show similar trend: the channel mobility decreases as the channel length increases [30]. These results suggest that the transistor performance is correlated with grain size.…”

Integrated amorphous and polycrystalline silicon thin-film transistors in a single silicon layer

“…The field-effect mobility of these poly-Si TFTs was 14 cm /Vs and the ON/current ratio was 10 (sample 8, Table II). With the self-aligned process flow discussed elsewhere [24], for the blanket hydrogen-plasma-treated poly-Si TFTs, higher field-effect mobility and better ON/OFF current ratios of 33 cm /Vs and 10 , and 75 cm /Vs and 10 for low temperature ( 600 C) and high temperature ( 1000 C) processes, respectively, can be achieved. With a laterally-seeded process flow, the performance of the low-temperature TFTs could be improved even further to achieve field-effect mobility as high as 75 cm /Vs and ON/OFF current ratio greater than 10 [24].…”

Leakage Current Reduction Techniques in Poly-Si TFTs for Active Matrix Liquid Crystal Displays: A Comprehensive Study

“…In other words, the crystallinity of poly-Si can be improved by adjusting the deposition pressure, leading to an improvement of the electrical properties of the TFTs [20], [21]. The advantages of SPC are high reproducibility, good roughness control, and uniformity [22]- [24].…”

“…In other words, the crystallinity of polysilicon can be improved by adjusting the deposition pressure leading to an improvement of the electrical properties of the TFTs [20], [21]. The advantages of SPC are high reproducibility, good roughness control and uniformity [22]- [24] Excimer-laser-annealing (ELA) is a promising laser induced crystallization (LIC) technique for TFT polysilicon layers [25]- [27], although it is a more expensive and a more difficult process to implement than the solid phase crystallization (SPC) process. In excimer-laser-annealing, a highly energetic radiation achieves the melting of the upper part of polysilicon layer.…”