Thermoelastic stresses and defect production in semiconductor-insulator structures at isothermic heating

Abstract

For semiconductor structure substrates with film coating disturbances we investigated thermoelastic stresses and their effect on defect production at isothermic heating. A developed mathematical model enables one to optimize the formation and annealing conditions for structures with film coating disturbances during annealing when manufacturing integrated microcircuits.

Optimization of Chamber Design and Rapid Thermal Processing Regimes for SiC Substrates by Temperature and Thermal Stress Distribution

“…where d is the thickness of substrate; a t is the effective absorptivity which depends on the substrate thickness, temperature, doping concentration and radiation spectrum of the heating source [7].…”

The influence of heating temperature and sizes of components upon stresses and defect formation in semiconductor structures under isothermal heating

“…Introducing defect formation criterion as τ to τ E ratio, we can define conditions and areas of structure, where dislocation generation takes place [13].…”

“…Stresses in the SiO 2 film can be defined within the model given in [14] using Si and SiO 2 physico-mechanical parameters [3]. In [13] stresses in the SiO 2 film under heating to 800°C were determined: σ int = −2.10⋅10 9 din/cm 2 ; σ th = 2.55⋅10 9 dyne/cm 2 ; σ f = 4.5⋅10 8 dyne/cm 2 .…”