Thermionic-emission-based barrier height analysis for precise estimation of charge handling capacity in CCD registers

Kawai, S.; Mutoh, N.; Teranishi, Nobukazu

doi:10.1109/16.628808

Cited by 15 publications

(6 citation statements)

References 3 publications

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“…This is because of thermionic emission and diffusion of carriers over the barrier in any realistic structure and the need for a practical storage time. It is estimated that an extra barrier height of about 0.5 volts (20kT ) is required to keep electrons in the well [65], [66] although thermionic emission occurs at all barrier heights and there is no absolute cut off for the process. Under illumination, it is possible that optical carrier generation balances emission across the barrier and a solarcell-like logarithmic dependence of full well as a function of illumination level might be realized [64].…”

Section: Full Wellmentioning

confidence: 99%

A Review of the Pinned Photodiode for CCD and CMOS Image Sensors

Fossum

Hondongwa

2014

IEEE J. Electron Devices Soc.

352

191

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Section: Full Wellmentioning

confidence: 99%

A Review of the Pinned Photodiode for CCD and CMOS Image Sensors

Fossum

Hondongwa

2014

IEEE J. Electron Devices Soc.

352

191

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“…Differently from other methods based on the thermoionic emission [4] or on 3D simulations [ 5 ] , our model is based on the comparison of the average electrostatic energy per electron with the amplitude of the smaller potential barrier responsible of the electron confinement. We can approximate the electrons' distribution as a sphere of radius R with uniform charge density.…”

Section: Discussionmentioning

confidence: 99%

Analysis and characterisation of the confining mechanism of the controlled-drift detector

Castoldi

Gatti

Guazzoni

et al. 1999

IEEE Trans. Nucl. Sci.

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The Controlled-Drift Detector is a recently designed position-sensing X-ray detector. It operates by switching between integration and drift mode. The basic idea is to generate potential wells within the otherwise linear drift potential. During the integration mode signal electrons are being accumulated within these wells. The removal of the barriers in an externally controlled way restores a uniform drift field that sweeps the electrons towards the readout anodes.The height of the confining barrier depends on the drift field and on the amplitude of the potential perturbation at the surface. An experimental study ' of the charge handling capability has been carried out as a function of the amplitude of the surface perturbation (up to 2.1 V) and as a function of the drift field (250-400 V/cm). The study provides a sensitive measurement of the actual potential barrier of the integration well in different operating conditions. A detailed analysis and characterisation of the mechanisms to confine the signal electrons in the 3D well is presented. For a drift field of 300 V/cm, storage of more than lo5 electrons in 180 x 180 pm2 pixels has been achieved with 1.67 V surface perturbation.

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“…The electron signal in the pixel continues to increase until either blooming occurs into the adjacent pixels in the vertical column or, as in a properly designed device, the excess electron signal charge spills over the B3 region into the LOD. The pixel is judged to be full, or at maximum charge capacity, when the difference in channel potential between the S1 and B3 regions measures 0.5 V. This value is found to correspond empirically to the onset of electron emission over barriers in CCD devices, for the time scales generally encountered during the imager operation 12 . Through integration of the electron density distribution obtained from three-dimensional solution to Poisson's equation (in which the electron Fermi level is manually adjusted, uniformly throughout the pixel, to produce a potential difference of 0.5 V between the S1 and B3 regions), the charge capacity of the pixel in the accumulation mode is found to be 64,000 electrons.…”

Section: Pixel Charge Capacitymentioning

confidence: 99%

An LOD with improved breakdown voltage in full-frame CCD devices

et al. 2005

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In full-frame image sensors, lateral overflow drain (LOD) structures are typically formed along the vertical CCD shift registers to provide a means for preventing charge blooming in the imager pixels. In a conventional LOD structure, the n-type LOD implant is made through the thin gate dielectric stack in the device active area and adjacent to the thick field oxidation that isolates the vertical CCD columns of the imager. In this paper, a novel LOD structure is described in which the n-type LOD impurities are placed directly under the field oxidation and are, therefore, electrically isolated from the gate electrodes. By reducing the electrical fields that cause breakdown at the silicon surface, this new structure permits a larger amount of n-type impurities to be implanted for the purpose of increasing the LOD conductivity. As a consequence of the improved conductance, the LOD width can be significantly reduced, enabling the design of higher resolution imaging arrays without sacrificing charge capacity in the pixels. Numerical simulations with MEDICI of the LOD leakage current are presented that identify the breakdown mechanism, while three-dimensional solutions to Poisson's equation are used to determine the charge capacity as a function of pixel dimension.

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Thermionic-emission-based barrier height analysis for precise estimation of charge handling capacity in CCD registers

Cited by 15 publications

References 3 publications

A Review of the Pinned Photodiode for CCD and CMOS Image Sensors

A Review of the Pinned Photodiode for CCD and CMOS Image Sensors

Analysis and characterisation of the confining mechanism of the controlled-drift detector

An LOD with improved breakdown voltage in full-frame CCD devices

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