Thermally enhanced 3 dimensional integrated circuit (TE3DIC) packaging

Abstract

Commercial packaging roadmaps clearly depict the imminence of chip stacking utilizing through silicon via (TSV) technology (commonly referred to as 3-dimensional integrated circuits (3DIC)) as a means to improve system performance by reducing routing lengths, latency, and drive power while increasing functionality per unit volume. Roadmaps and packaging research focus areas also depict complex 3DIC and packaging architecture concepts to include heterogeneous materials, components and features [1][2]. This added diversity often exacerbates physical proximity effects such as thermal and electromagnetic (EM) coupling. To reduce unwanted thermal and EM coupling, we propose interleaving 25µm thick, flexible, high thermal conductivity (1600 W/m·K, in-plane) pyrolytic graphite sheets (PGS) [3] into 3DIC stacks. The PGS provides passive parallel thermal paths from each die to the package heat spreader with potential significant reduction in overall package thermal resistance ( JC ). This also provides design flexibility to thermally decouple sensitive components within the package from intermittent power sources by thermal routing. Interleaving PGS is also expected to impart EM shielding benefits between die and serve to reduce overall package emissions. This paper focuses on potential junction-to-case thermal resistance improvements of a Thermally Enhanced 3-Dimensional Integrated Circuit (TE3DIC) packaging solution. By utilizing a path-finding set of thermal models of a TE3DIC BGA package, design parameters are adjusted to assess various cases, promote design intuition, and ultimately lead to a final test vehicle design. This test vehicle includes three TSV die with both uniform and localized (fireball) Ni80Cr20 heater traces and include resistive platinum temperature sensors. These die are copper pillar bonded with PGS interleaved and flip chip soldered to a 37mm BGA carrier. The perimeter of the PGS is bonded to a terraced copper heat spreader. Detailed modeling estimates a 44% reduction in package thermal resistance with PGS interleaves in a three die stack compared with a similar direct bonded die stack. Reductions are greater for 3DIC designs with copper pillar bonding compared to covalently bonded die stacks.

Examining Carbon Nanofibers: Properties, growth, and applications

“…in fact, much focus on the packaging industry has been on heat spreading using materials such as graphite. despite the successful implementation of heat spreaders, removing heat from the chips to the package and cnF is expected to play a key role in the vertical extraction of heat from the chip to the package [38].…”

Thermal performance of 3D ICs: Analysis and alternatives

“…Inplane thermal conductivity can be up to 2000 W/m·K (i.e., 5x higher than that of copper). Authors in [22] recently proposed the use of PG to reduce the junction-to-case thermal resistance in 3D IC packages. PG layers are interleaved into the 3D stack and connected to a terraced heat spreader, serving as thermal paths to convey heat from each die to the heat spreader.…”

Cooling from the bottom side (laminate (substrate) side) of a three-dimensional (3D) chip stack

“…In this section, locating a graphite sheet in the joint (interconnection) layer between a bottom chip and a laminate is proposed [4]. Firstly, as shown in Figure 3, the cooling structure in which a graphite sheet is connected to a lid (a heat spreader) is considered.…”