Thermal vs Energy Optimization for DVFS-Enabled Processors in Embedded Systems

Liu, Yongpan; Yang, Huazhong; Dick, Robert P.; Wang, H.; Shang, Li

doi:10.1109/isqed.2007.158

Cited by 105 publications

(94 citation statements)

References 18 publications

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“…Liu et al [16] formulate the problem of assigning voltages to tasks on an MPSoC under thermal constraints as a non linear programming problem. They observe that optimizing purely for energy can result in higher peak temperatures.…”

Section: Related Workmentioning

confidence: 99%

“…In this paper, we address the problem of minimizing the peak temperature of a set of periodic heterogenous tasks executing on a processor under timing constraints. The existing solutions to similar problems [22], [16] employ voltage scaling as the only mechanism for temperature management. We observe that task sequencing has significant impact on the thermal profile and the peak temperature.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…In general, tasks exhibit significant variation in terms of their power consumption characteristics [18], [16]. This is because power consumption depends on the circuit activity factor that can vary significantly across tasks [16]. Moreover, modern low-power processors engage aggressive clock gating and static power saving techniques [6], [9], [8] where the idle functional units are either clock gated or completely switched off.…”

Section: Introductionmentioning

confidence: 99%

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Temperature aware task sequencing and voltage scaling

Jayaseelan

Mitra

2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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Abstract-On-chip power density and temperature are rising exponentially with decreasing feature sizes. This alarming trend calls for temperature management at every level of system design. In this paper, we propose task sequencing as a powerful and complimentary mechanism to voltage scaling in improving the thermal profile of an embedded system executing a set of periodic heterogenous tasks under timing constraints. We first derive the peak temperature of a repeating task sequence analytically and develop a heuristic to construct the task sequence that minimizes the peak temperature. Experimental evaluation shows that our task sequencing heuristic achieves peak temperature within 0.5 o C of the optimal solution and 7.47 o C lower, on an average, compared to the worst sequence for a large range of embedded task sets. We also propose an iterative algorithm that combines task sequencing with voltage scaling to further lower the peak temperature while satisfying the timing constraints. For embedded task sets, our combined task sequencing and voltage scaling approach achieves, on an average, 2.1 o C − 6.94 o C reduction in peak temperature compared to voltage scaling alone.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Temperature aware task sequencing and voltage scaling

Jayaseelan

Mitra

2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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“…There have been extensive researches conducted on power/energy consumption reduction at different design abstraction levels, from logical level, circuit level, architecture level, and all the way to the system levels [57,82,91,115,117,80,76].…”

Section: Power Reduction Techniquesmentioning

confidence: 99%

Practical Dynamic Thermal Management on Intel Desktop Computer

Quan

Liu

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Professor Gang Quan, Major ProfessorFueled by increasing human appetite for high computing performance, semiconductor technology has now marched into the deep sub-micron era. As transistor size keeps shrinking, more and more transistors are integrated into a single chip. This has increased tremendously the power consumption and heat generation of IC chips. The rapidly growing heat dissipation greatly increases the packaging/cooling costs, and adversely affects the performance and reliability of a computing system. In addition, it also reduces the processor's life span and may even crash the entire computing system. Therefore, dynamic thermal management (DTM) is becoming a critical problem in modern computer system design.Extensive theoretical research has been conducted to study the DTM problem.However, most of them are based on theoretically idealized assumptions or simplified models. While these models and assumptions help to greatly simplify a complex problem and make it theoretically manageable, practical computer systems and applications must deal with many practical factors and details beyond these models or assumptions.The goal of our research was to develop a test platform that can be used to validate theoretical results on DTM under well-controlled conditions, to identify the limitations of existing theoretical results, and also to develop new and practical DTM techniques. This dissertation details the background and our research efforts in this v endeavor. Specifically, in our research, we first developed a customized test platform based on an Intel desktop. We then tested a number of related theoretical works and examined their limitations under the practical hardware environment. With these limitations in mind, we developed a new reactive thermal management algorithm for single-core computing systems to optimize the throughput under a peak temperature constraint. We further extended our research to a multicore platform and developed an effective proactive DTM technique for throughput maximization on multicore processor based on task migration and dynamic voltage frequency scaling technique. The significance of our research lies in the fact that our research complements the current extensive theoretical research in dealing with increasingly critical thermal problems and enabling the continuous evolution of high performance computing systems.

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Temperature- and Energy-Constrained Scheduling

Wang

Mishra

Ranka

2012

Dynamic Reconfiguration in Real-Time Systems

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Along with the performance improvement in state-of-art microprocessors, power densities are rising rapidly due to the fact that feature size scales faster than voltages [113]. In the last 5 years, though the processor frequency has only improved by 30%, the power density is more than doubled and expected to reach over 250 W/cm 2 [32]. Since energy consumption is converted into heat dissipation, high heat flux increases the on-chip temperature. The "hot spot" on current microprocessor die, caused by nonuniform peak power distribution, could reach up to 120 • C [14]. This trend is observed in both desktop and embedded processors [127, 158].Thermal increase will lead to reliability and performance degradation since CMOS carrier mobility is dependent on the operating temperature. High temperature can result in more frequent transient errors or even permanent damage. Industrial studies have shown that a small difference in operating temperature (10-15 • C) can make 2 times difference in the device lifespan [127]. Yeh et al. [150] also estimate that more than half of the electronic failures are caused by over-heated circuits. Furthermore, leakage power is exponentially proportional to temperature, which potentially results in more thermal runaway [141]. Studies also show that cooling cost increases super-linearly with the thermal dissipation [39].Since high on-chip thermal dissipation has severe detrimental impact, we have to control the instantaneous temperature so that it does not go beyond a certain threshold. Thermal management schemes at all levels of system design are widely studied for general-purpose systems. However, in the context of embedded systems, traditional packaging and cooling solutions are not applicable due to the limits on device size and cost. Moreover, embedded systems normally have limited energy budgets. Multitasking systems with real-time constraints add another level of difficulty since tasks have to meet their deadlines. Since such systems normally have well-defined functionality, this multi-objective problem admits design-time algorithms.DVS is acknowledged as one of the most efficient techniques both in energy optimization [21] and temperature management [158]. In existing literatures, temperature (energy)-constrained means that there is a temperature threshold W. Wang et al., Dynamic Reconfiguration in Real-Time Systems: Energy, Performance, and Thermal Perspectives, Embedded Systems, DOI 10.1007/978-1-4614-0278-7 7, © Springer Science+Business Media New York 2013 165 166 7 Temperature-and Energy-Constrained Scheduling(energy budget) which cannot be exceeded, while temperature (energy)-aware means that there is no constraint but maximum instantaneous temperature (total energy consumption) needs to be minimized. In this chapter, we examine a formal method based on model checking for temperature-and energy-constrained (TCEC) scheduling problems in multitasking systems. The classical timed automata [1] is extended with notions of task scheduling, voltage scaling, system temperature and ene...

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Thermal vs Energy Optimization for DVFS-Enabled Processors in Embedded Systems

Cited by 105 publications

References 18 publications

Temperature aware task sequencing and voltage scaling

Temperature aware task sequencing and voltage scaling

Practical Dynamic Thermal Management on Intel Desktop Computer

Temperature- and Energy-Constrained Scheduling

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