Thermal SPICE Modeling of FinFET and BEOL Considering Frequency-Dependent Transient Response, 3-D Heat Flow, Boundary/Alloy Scattering, and Interfacial Thermal Resistance

Chung, Chia-Che; Lin, Hsin-Cheng; Wan, Weier; Yang, Meng-Ta; Liu, C. W.

doi:10.1109/ted.2019.2912426

Cited by 21 publications

(2 citation statements)

References 15 publications

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“…The flip-chip package is a package type with the shortest path from chip devices to circuit boards, so it is known that high-speed operation is possible due to low-resistance components and noise. The thermal characteristics of the MoS 2 -FET for each region and the boundary conditions (this time the thermal resistivity) considering the package type are summarized in Table . , The thermal properties are described with the thermal conductivity (or resistivity) of each region considering the MoS 2 layer thickness, MOL/BEOL wiring characteristics in an integrated circuit, and the connecting area considering the package type.…”

Section: Circuit-level Analysis Of Single/multilayer Mos2-fet At Vari...mentioning

confidence: 99%

Investigation of Optimal Architecture of MoS₂ Channel Field-Effect Transistors on a Sub-2 nm Process Node

Park

Jung

Kwon

et al. 2023

ACS Appl. Electron. Mater.

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In this work, performance comparison of various architectures of field-effect transistors (FETs) introduced with transition metal dichalcogenide (TMDC) MoS2 channels, which is attracting attention as one of the technologies that will enable beyond-silicon technology, was performed. By performing circuit-level benchmark for dynamic logic circuit operation in sub-2 nm dimension, it is observed that the optimal FET structure differs according to MoS2 layer numbers. When two or more multilayer MoS2 is applied to a double-gate and multistacked channel FET structure, the capacitance increases due to the increase in structure complexity, but the improvement of the current is greater, and the circuit operation speed increases. It is similar to the scaling-down trend of silicon-based FETs. However, in the case of monolayer MoS2, a simple single-gate planar FET structure shows optimal circuit characteristics, which is analyzed to be due to the excellent short-channel effect immunity of the monolayer MoS2 channel and small parasitic capacitance. Layout effects such as fan-out numbers and wiring load in integrated logic circuits were also investigated in various MoS2-FET structures. In addition, reliability analysis was performed through electrothermal simulation of thermal issues related to the multigate transistor structure.

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Section: Circuit-level Analysis Of Single/multilayer Mos2-fet At Vari...mentioning

confidence: 99%

Investigation of Optimal Architecture of MoS₂ Channel Field-Effect Transistors on a Sub-2 nm Process Node

Park

Jung

Kwon

et al. 2023

ACS Appl. Electron. Mater.

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“…When thermal flux is applied across an interface, ITR causes a finite temperature discontinuity. Low ITR is technologically important for heat dissipation in integrated circuits [4], whereas high ITR is critical for engine turbine protection [5,6]. The growing interest in space exploration necessitates developing special material systems that can withstand high temperatures and have high ITR.…”

Section: Introductionmentioning

confidence: 99%

Predicting Interfacial Thermal Resistance by Ensemble Learning

Chen

Tian

et al. 2021

Computation

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Interfacial thermal resistance (ITR) plays a critical role in the thermal properties of a variety of material systems. Accurate and reliable ITR prediction is vital in the structure design and thermal management of nanodevices, aircraft, buildings, etc. However, because ITR is affected by dozens of factors, traditional models have difficulty predicting it. To address this high-dimensional problem, we employ machine learning and deep learning algorithms in this work. First, exploratory data analysis and data visualization were performed on the raw data to obtain a comprehensive picture of the objects. Second, XGBoost was chosen to demonstrate the significance of various descriptors in ITR prediction. Following that, the top 20 descriptors with the highest importance scores were chosen except for fdensity, fmass, and smass, to build concise models based on XGBoost, Kernel Ridge Regression, and deep neural network algorithms. Finally, ensemble learning was used to combine all three models and predict high melting points, high ITR material systems for spacecraft, automotive, building insulation, etc. The predicted ITR of the Pb/diamond high melting point material system was consistent with the experimental value reported in the literature, while the other predicted material systems provide valuable guidelines for experimentalists and engineers searching for high melting point, high ITR material systems.

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Anisotropy Enhancing Vertically Aligned Silicon-Germanium Nanowire

Mohamedyaseen

Kumar²,

Kavitha³

et al. 2022

Silicon

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Thermal SPICE Modeling of FinFET and BEOL Considering Frequency-Dependent Transient Response, 3-D Heat Flow, Boundary/Alloy Scattering, and Interfacial Thermal Resistance

Cited by 21 publications

References 15 publications

Investigation of Optimal Architecture of MoS₂ Channel Field-Effect Transistors on a Sub-2 nm Process Node

Investigation of Optimal Architecture of MoS₂ Channel Field-Effect Transistors on a Sub-2 nm Process Node

Predicting Interfacial Thermal Resistance by Ensemble Learning

Anisotropy Enhancing Vertically Aligned Silicon-Germanium Nanowire

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Thermal SPICE Modeling of FinFET and BEOL Considering Frequency-Dependent Transient Response, 3-D Heat Flow, Boundary/Alloy Scattering, and Interfacial Thermal Resistance

Cited by 21 publications

References 15 publications

Investigation of Optimal Architecture of MoS2 Channel Field-Effect Transistors on a Sub-2 nm Process Node

Investigation of Optimal Architecture of MoS2 Channel Field-Effect Transistors on a Sub-2 nm Process Node

Predicting Interfacial Thermal Resistance by Ensemble Learning

Anisotropy Enhancing Vertically Aligned Silicon-Germanium Nanowire

Contact Info

Product

Resources

About

Investigation of Optimal Architecture of MoS₂ Channel Field-Effect Transistors on a Sub-2 nm Process Node

Investigation of Optimal Architecture of MoS₂ Channel Field-Effect Transistors on a Sub-2 nm Process Node