Thermal response measurements for semiconductor device die attachment evaluation

Oettinger, Frank F.; Gladhill, Richard

doi:10.1109/iedm.1973.188645

Cited by 12 publications

(3 citation statements)

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“…It can be seen that with the transient technique used in this study a void covering roughly 35 percent of the die area produced a 27.5 percent increase in the temperature rise over what it would be had there been no void. As had been noted in the previous study [51] , steady-state thermal resistance measurements on these devices were much less sensitive; only a 10-percent increase in steady-state temperature rise was produced by a void covering 35 percent of the die area. Substantial variations in the quality of the die attach were observed on some of these devices with the use of radiographic x-ray techniques.…”

Section: Integrated Circuit Die Attachment Evaluationsupporting

confidence: 50%

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Semiconductor measurement technology

Bullis¹

1979

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This progress report describes NBS activities directed toward the development of methods of measurement for semiconductor materials, process control, and devices.Both in-house and contract efforts are included.The emphasis is on silicon device technologies. Principal accomplishments during this reporting period included (1) refinement and extension of the analysis of the nondestructive, photovoltaic method for measuring radial resistivity variation of silicon slices; (2) development of a donor-addition technique for testing for the presence of X-levels in indium-doped silicon;(3) development of a precision, wet chemical etching procedure for use in conjunction with x-ray photoelectron spectroscopy for profiling silicon dioxide-silicon interfaces; (4) completion of thermodynamic calculations of equilibrium sodium density in oxidation atmospheres contained in polycrys t al 1 ine silicon tubes; (5) initial extensions of the line-width measurement procedure to partially transparent and reflecting specimens and to submicrometer dimensions; and (6) completion of the development of a test pattern for characterizing a large-scaleintegrat ion, silicon-on-sapphire process. Also reported is other ongoing work on materials characterization by electrical and physical analysis methods, materials and procedures for wafer processing, photolithography, test patterns, and device inspection and test procedures.Supplementary data concerning staff and publications are included as appendices.

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Section: Integrated Circuit Die Attachment Evaluationsupporting

confidence: 50%

“…400-29, pp. [50][51][52], and 400-36, pp. [42][43][44] [32], although the optical system parameters have remained the same.…”

Section: )mentioning

confidence: 99%