2019
DOI: 10.1109/tcpmt.2019.2901297
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Thermal Performances of an Improved Package for Cryocooled Josephson Standards

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Cited by 7 publications
(8 citation statements)
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References 28 publications
(26 reference statements)
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“…Preliminary tests of the bias techniques presented in Section III have been carried out. The experimental setup included a conventional 13-bit PJVS array made of SNIS junctions [17], operated in a Cryomech PT-410 1 two-stage pulse-tube refrigerator with 1 W cooling power at 4.2 K. The PJVS chip was embedded in a special cryopackage similar to that described in [28], suitably tightened to the cryocooler coldplate (Fig. 3).…”
Section: Methodsmentioning
confidence: 99%
“…Preliminary tests of the bias techniques presented in Section III have been carried out. The experimental setup included a conventional 13-bit PJVS array made of SNIS junctions [17], operated in a Cryomech PT-410 1 two-stage pulse-tube refrigerator with 1 W cooling power at 4.2 K. The PJVS chip was embedded in a special cryopackage similar to that described in [28], suitably tightened to the cryocooler coldplate (Fig. 3).…”
Section: Methodsmentioning
confidence: 99%
“…Proper operation of a Josephson standard in cryocooler is always a challenging task, owing to the tight thermalization requirements [30,31] alongside the need of supplying non negligible dc and rf power for proper operation. We addressed the issue of designing an optimized cryopackage for maximizing the thermal contact between the chip and the cooling surface [32]. It takes advantage of a soft indium foil with a corrugate surface for optimal transmission, achieved by filling the voids between rough surfaces.…”
Section: Pulsed Standards Toward Rfmentioning
confidence: 99%
“…The sourcemeter is floating from ground by means of an isolation transformer to avoid interference between simultaneous power and JJ apparent resistance measurements. [8] and cooled with a two-stage pulse-tube cryocooler (Cryomech PT-410 ‡), as shown in Figure 4. Two calibrated silicon diode sensors are employed to determine the temperature of cryocooler coldplate and chip carrier, which should be approximately equal as long as these are in good thermal contact.…”
Section: Josephson Chip and Cryogenic Equipmentmentioning
confidence: 99%
“…The residual thermal resistance is not low enough in the most demanding conditions and particular care is required in the design of a chip carrier to reduce thermal gradients, mainly at the interfaces between solid bodies. For JVSs working in the high-vacuum environment of a cryocooler, special cryopackages have been designed [6][7][8][9], exhibiting thermal resistances between chip and cold heat sink of few kelvin per watt. The case of JVS is particularly interesting and challenging: power levels of some tens of milliwatt are generally dissipated within a JVS, possibly causing its actual temperature to differ from that measured with the the sensor by hundreds of millikelvin.…”
Section: Introductionmentioning
confidence: 99%
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