Thermal influence on the energy efficiency of workload consolidation in many-core architectures

IEEE Trans. Cloud Comput.

et al. 2020

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New pricing policies are emerging where cloud providers charge resource provisioning based on the allocated CPU frequencies. As a result, resources are offered to users as combinations of different performance levels and prices which can be configured at runtime. With such new pricing schemes and the increasing energy costs in data centres, balancing energy savings with performance and revenue losses is a challenging problem for cloud providers. CPU frequency scaling can be used to reduce power dissipation, but also impacts VM performance and therefore revenue. In this paper, we firstly propose a non-linear power model that estimates power dissipation of a multi-core PM and secondly a pricing model that adjusts the pricing based on the VM's CPU-boundedness characteristics. Finally, we present a cloud controller that uses these models to allocate VMs and scale CPU frequencies of the PMs to achieve energy cost savings that exceed service revenue losses. We evaluate the proposed approach using simulations with realistic VM workloads, electricity price and temperature traces and estimate energy savings of up to 14.57%.

Section: Related Workmentioning

confidence: 99%

Performance-Based Pricing in Multi-Core Geo-Distributed Cloud Computing

Lučanin

Pietri

IEEE Trans. Cloud Comput.

et al. 2020

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“…Hence, the silicon temperature causes an exponential increase in leakage currents [6]. Moreover, when lowering the supply voltage of integrated circuits, the subthreshold leakage current increases which also increases the dissipated static power [2], [24].…”

Section: A Dynamic Voltage and Frequency Scaling (Dvfs)mentioning

confidence: 99%

Accurate Energy Modelling for Many-Core Static Schedules

2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing

Keller

Eitschberger

et al. 2015

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Static schedules can be a preferable alternative for applications with timing requirements and predictable behavior since the processing resources can be more precisely allocated for the given workload. Unused resources are handled by power management systems to either scale down or shut off parts of the chip to save energy. In order to efficiently implement power management, especially in many-core systems, an accurate model is important in order to make the appropriate power management decisions at the right time. For making correct decisions, practical issues such as latency for controlling the power saving techniques should be considered when deriving the system model, especially for fine timing granularity. In this paper we present an accurate energy model for many-core systems which includes switching latency of modern power saving techniques. The model is used when calculating an optimal static schedule for many-core task execution on systems with dynamic frequency levels and sleep state mechanisms. We create the model parameters for an embedded processor, and we validate it in practice with synthetic benchmarks on real hardware.

“…We acknowledge these findings in our work and aim to realize the outcomes by utilizing DPM and DVFS to obtain minimal power while keeping the QoS guarantees defined in the applications. Furthermore we also take the temperature into account, which significantly affects the static power dissipation [5]. We also create our power model specifically for a given CPU type, which gives us the total power dissipation as a function of resource usage.…”

Section: Related Workmentioning

confidence: 99%

“…Depending on the CPU architecture and the manufacturing technology this relation varies, but with current clock frequency levels, is it usually very energy inefficient to execute on high clock frequencies [24], [17]. It is also (usually) inefficient to execute on very low clock frequencies [5] since the execution time becomes large and the static power is dissipated during the whole execution.…”

Section: Qos and Parallelism Aware Strategymentioning

confidence: 99%

“…Power trace from the parallel application using default CFS and with power optimizer output for the optimized case compared to Figure 10. This is because the static power increase when using more cores is almost identical to the dynamic power decrease of reducing the clock frequency -this is an occurring phenomenon as systems run on very low clock frequencies with many cores [5]. The situation could be improved by fine tuning the power model to enable higher precision.…”

Section: Parallel Applicationmentioning

confidence: 99%

See 1 more Smart Citation

Energy efficiency and performance management of parallel dataflow applications

Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing

Nogues

Pelcat

et al. 2014

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