Thermal-Driven Floorplanning for Fixed Outline Layouts

Abstract

In the nano-scale era, chip temperature has gained a lot of importance due to various reasons. Localized high temperatures in certain regions, commonly known as hotspots, directly affect the performance and reliability of the chip. The proposed work concentrates on temperature-driven floorplanning of chips because incorporating cooling techniques may lead to increase in cost. The proposed approach attempts to evenly distribute power dense components across the chip area in order to suppress hotspots and at the same time generate a layout with aspect ratio nearly 1, as is required in the present day floorplanning scenario. The positions of the blocks in the layout are generated using Boolean Satisfiability (SAT). Apart from peak temperature, wirelength being an important cost factor is also taken into consideration. The proposed technique is successful in decreasing the wirelength and peak temperature for large GSRC, MCNC and IBM HB[Formula: see text] benchmarks.