Thermal cycling reliability of Cu/SnAg double-bump flip chip assemblies for 100 μm pitch applications

Abstract

A thick Cu column based double-bump flip chip structure is one of the promising alternatives for fine pitch flip chip applications. In this study, the thermal cycling (T/C) reliability of Cu/SnAg double-bump flip chip assemblies was investigated, and the failure mechanism was analyzed through the correlation of T/C test and the finite element analysis (FEA) results. After 1000 thermal cycles, T/C failures occurred at some Cu/SnAg bumps located at the edge and corner of chips. Scanning acoustic microscope analysis and scanning electron microscope observations indicated that the failure site was the Cu column/Si chip interface. It was identified by a FEA where the maximum stress concentration was located during T/C. During T/C, the Al pad between the Si chip and a Cu column bump was displaced due to thermomechanical stress. Based on the low cycle fatigue model, the accumulation of equivalent plastic strain resulted in thermal fatigue deformation of the Cu column bumps and ultimately reduced the thermal cycling lifetime. The maximum equivalent plastic strains of some bumps at the chip edge increased with an increased number of thermal cycles. However, equivalent plastic strains of the inner bumps did not increase regardless of the number of thermal cycles. In addition, the z-directional normal plastic strain ε22 was determined to be compressive and was a dominant component causing the plastic deformation of Cu/SnAg double bumps. As the number of thermal cycles increased, normal plastic strains in the perpendicular direction to the Si chip and shear strains were accumulated on the Cu column bumps at the chip edge at low temperature region. Thus it was found that the Al pad at the Si chip/Cu column interface underwent thermal fatigue deformation by compressive normal strain and the contact loss by displacement failure of the Al pad, the main T/C failure mode of the Cu/SnAg flip chip assembly, then occurred at the Si chip/Cu column interface shear strain deformation during T/C.

Effects of Bonding Temperature and Pressure on the Electrical Resistance of Cu/Sn/Cu Joints for 3D Integration Applications

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The FEM analysis of stress and strain in stacked solder bump under power load

“…Ho-Young Son [1] had made 220 stacked Cu/SnAg solder bumps on the memory chip, after 1000 hours 85 /85%RH reliability tests and 1000 cycles thermal cycle test between -55 +125 showed no failure. Kathy Wei Yan [2] had made a double solder joint. After the thermal cycle test it showed that the reliability of stacked solder ball is 1.5 times than single layer solder joints.…”

Mask and mask-less injection molded solder (IMS) technology for fine pitch substrate bumping

“…Recently, many researchers have reported that copper column flip chip joints can handle higher current density and have stronger resistance against electromigration induced failure [1][2][3]. The thick copper die bump helps to move the current crowding region from the solder to the copper in a flip chip joint [4].…”