Thermal Cycle Reliability of 3D Chip Stacked Package Using Pb-free Solder Bumps: Parameter Study by FEM Analysis

Noritake, C.; Limaye, Paresh; González, Mario; Vandevelde, Bart

doi:10.1109/esime.2006.1644002

Cited by 14 publications

(5 citation statements)

References 5 publications

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“…The problems are however quite similar to the standard packaging and hybridization reliability issues: mismatch of coefficient of thermal expansion of different materials, and as a consequence stress build-up and failure through e.g. delamination, crack initiation [4]. Careful design driven by thermo-electrical simulations can solve most of the problems.…”

Section: Risksmentioning

confidence: 94%

Recent Advances in 3D Integration at IMEC

et al. 2006

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IMEC is focusing its 3D-integration technology developments in 3 distinct directions: 3D-System-in-a-Package (3D-SiP), 3D-Wafer-Level-Packaging (3D-WLP) and 3D-Stacked-IC (3D-SiC). First, the background of these separate approaches will be given. Next the materials and technologies involved, the typical characteristics and the ongoing developments will be discussed. Finally, the roadmap for the 3D-integration in IMEC will be presented.

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Section: Risksmentioning

confidence: 94%

Recent Advances in 3D Integration at IMEC

et al. 2006

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“…The reference temperature was assumed to be 165 ℃ . Furthermore, it is assume that surface of Si chips is perfectly flat, although the surface of Si chips may have some grinding and thin film deposition [6]. …”

Section: Finite Element Modelingmentioning

confidence: 99%

“…Fig.16 shows the maximum stress with different types underfill and without underfill. It's obvious that maximum stress of submodel is decreased greatly when the underfill is applied, which is due to the strain redistribution by underfill [6]. The reduction is the highest (27.5%) when using UF2, because the CTE mismatch of UF2 is smaller than UF3 and the Young's modulus of UF2 is lower than that of UF1.…”

Section: Effect Of Pi and Alsicu Pad Materials Propertiesmentioning

confidence: 99%

Board level WLCSP 3D thermal stress analysis by submodeling of FEA

Hong

Wang

2010

2010 11th International Conference on Electronic Packaging Technology &Amp; High Density Packaging

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Wafer level Chip Scale Package (WLCSP) fulfills the demand for small, light, and portable handheld electronic devices, and it is one of the most advanced packaging concepts. When the WLCSP was assembled on board level, the connection, i.e. solder joints are generally the critical and challenging issue for the whole device's reliability. In addition to the shape and material of solder joints, the material and structures around the solder joints, such as underfill material, under bumper metal (UBM) and passivation layers can affect the connection's stress field under thermal loadings. In this investigation, the on board level WLCSP with Sn-Ag-Cu solder bump joints was built in 3D model and was analyzed by finite element method. The global model was simulated under one thermal cycling loading according to JEDEC standard. Owing to the ultra-thin thickness of UBM and passivation layers, the submodeling method was used in the finite element analysis to show the detail of stress distribution in the small structures near solder joints. When the structure sizes and material properties of solder joints, underfill and UBM were varied, the parametric analysis showed the trend of the stresses changing in the WLCSP. On the basis of analysis, the possible failure sites and optimization suggestions were obtained.

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“…The traditional interconnections reliability of the BGA, bump, and micro-bump still exists in the advanced 3D packaging design. Noritake [9] investigated the reliability of 3D chip stacked package by FEM simulation and showed that the failure position is expected the top part of the critical solder bump jointing the lower chip and the PCB during a thermal cycle test. Hossain [10] performed a finite element analysis based study for estimating accelerated temperature cycling solder joint characteristic fatigue life of different stack die architecture on chip scale ball grid array package.…”

Section: Introductionmentioning

confidence: 99%

The Reliability of Solder Joints in Fine Pitch 3-D Stack Package by Taguchi Method

Chen

Liu²,

Chen

2012

AMM

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To achieve high density and high performance, through-Silicon Vias (TSVs) have recently aroused much interest because it is a key enabling technology for three-dimensional (3-D) integrated circuit stacking and silicon interposer technology. In this study, a 3-D 1/8th symmetrical nonlinear finite element model of a stack die TSV package was developed using ANSYS finite element simulation. The model was used to optimize the package for robust design and to determine design rules to enhance 3-D stack package in view of bump reliability. An L8(2×7) Taguchi matrix was developed to investigate the effects of interposer thickness, TSV diameter, insulation (SiO2) thickness, chip thickness, substrate thickness, bump height, and bump diameter on bumps reliability. A temperature cycling test in the range of 0 °C to 100 °C was conducted by three cycles. The mechanical property of SAC leadless solder included time independent plastic and time dependent creep behaviors. The parameter of inelastic strain range of the third cycle was used to evaluate the bump life prediction. Two levels were chosen for each parameter to cover the ranges of interest. The results show that the smaller insulation (SiO2) and substrate thickness and the larger dimension for the other factors provide the best combination. These could be used as guides for further similar 3-D stack packages design.

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Thermal Cycle Reliability of 3D Chip Stacked Package Using Pb-free Solder Bumps: Parameter Study by FEM Analysis

Cited by 14 publications

References 5 publications

Recent Advances in 3D Integration at IMEC

Recent Advances in 3D Integration at IMEC

Board level WLCSP 3D thermal stress analysis by submodeling of FEA

The Reliability of Solder Joints in Fine Pitch 3-D Stack Package by Taguchi Method

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