Thermal characterization and simulation study of 2.5D packages with multi-chip module on through silicon interposer

Zhang, H. Y.; Zhang, X. W.; Lau, Boon Long; Lim, San Hua; Liu, Ding; Yu, Mingbin; Lee, Y. J.

doi:10.1109/eptc.2013.6745743

Cited by 7 publications

(3 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…FCBGA (see Figure 1 a) is particularly common in telecom, workstation, and computer applications due to its superior bandwidth and electrical performance. However, as the speed and I/O count of high-power packages increase, thermal dissipation control and management poses a critical concern [ 5 , 6 , 7 ]. Most of the heat generated by the chip is transferred to the printed circuit board (PCB) [ 8 ].…”

Section: Introductionmentioning

confidence: 99%

Reliability Evaluation of Board-Level Flip-Chip Package under Coupled Mechanical Compression and Thermal Cycling Test Conditions

et al. 2023

View full text Add to dashboard Cite

Flip Chip Ball Grid Array (FCBGA) packages, together with many other heterogeneous integration packages, are widely used in high I/O (Input/Output) density and high-performance computing applications. The thermal dissipation efficiency of such packages is often improved through the use of an external heat sink. However, the heat sink increases the solder joint inelastic strain energy density, and thus reduces the board-level thermal cycling test reliability. The present study constructs a three-dimensional (3D) numerical model to investigate the solder joint reliability of a lidless on-board FCBGA package with heat sink effects under thermal cycling testing, in accordance with JEDEC standard test condition G (a thermal range of −40 to 125 °C and a dwell/ramp time of 15/15 min). The validity of the numerical model is confirmed by comparing the predicted warpage of the FCBGA package with the experimental measurements obtained using a shadow moiré system. The effects of the heat sink and loading distance on the solder joint reliability performance are then examined. It is shown that the addition of the heat sink and a longer loading distance increase the solder ball creep strain energy density (CSED) and degrade the package reliability performance accordingly.

show abstract

Section: Introductionmentioning

confidence: 99%

Reliability Evaluation of Board-Level Flip-Chip Package under Coupled Mechanical Compression and Thermal Cycling Test Conditions

et al. 2023

View full text Add to dashboard Cite

show abstract

“…• C, the performance/latency is degraded by the increment in the number of DRAM refreshes (around 50% more refreshes every 10 • C of temperature increment), due to the leakage of charge on each DRAM cell [56]. DRAM high temperature problems are particularly exacerbated on multi-layer chips (2.5D and 3D chips) [57,58] where restrictions in space and energy consumption are tight, power densities are higher, and CPU and memory temperatures are highly correlated. Most of today's CPU and memory chips are embedded with built-in thermal sensors, and they will shut down automatically when the temperature exceeds a pre-determined threshold [59].…”

Section: 23mentioning

confidence: 99%

“…CPU Thermal Model. (2.5D fashion) may present a considerable thermal conductance among them due to the heat dissipation of each chip through the interposer[57]. In addition, the model ofFig.…”

mentioning

confidence: 99%