1996
DOI: 10.1016/s0924-4247(97)80109-4
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Thermal buckling of silicon capacitive pressure sensor

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Cited by 17 publications
(11 citation statements)
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“…[112][113][114] Several papers have explored out-of-plane buckling as a prospective sensing mechanism. [115][116][117][118][119] It should also be mentioned that theoretical studies have recognized buckling as a possible sensing mechanism that is incredibly sensitive, but has a very small sensing range due to the discrete nature of buckling. [115,116] Sensitivity could be an order of magnitude higher than that of conventional linear transduction, such as microcantilevers, with micrometer deflections over incredibly small ranges.…”
Section: Polymeric Thermal-buckling-based Sensor Arraysmentioning
confidence: 99%
“…[112][113][114] Several papers have explored out-of-plane buckling as a prospective sensing mechanism. [115][116][117][118][119] It should also be mentioned that theoretical studies have recognized buckling as a possible sensing mechanism that is incredibly sensitive, but has a very small sensing range due to the discrete nature of buckling. [115,116] Sensitivity could be an order of magnitude higher than that of conventional linear transduction, such as microcantilevers, with micrometer deflections over incredibly small ranges.…”
Section: Polymeric Thermal-buckling-based Sensor Arraysmentioning
confidence: 99%
“…In addition, our process induces a minimal stress on both wafers, as the total thermal expansion of Si and Pyrex wafers of same thickness is equal when cooled over the 270 to 20 C range. 14 Moreover, a process temperature less than 300 C allows metals to remain functional after the bonding process, which is a prerequisite for electronics-to-microfluidics integration. 9, 15 We have tested specially designed pad-to-pad electrode structures in devices fabricated with this technology and found that the electrodes were functional with 1.5% coefficient of variation in measured DC resistance (see ESI, Fig.…”
Section: Resultsmentioning
confidence: 99%
“…Next, wafers were bonded at 280 ºC during 40 minutes under vacuum with a tool pressure of 1000 mbar (Suss SB6 vacuum bonder). Although parylene bonding with lower temperatures is possible [1][2][3], the selection of the temperature is done to be close (± 20 ºC) to stress-free bonding temperature of 280 ºC for silicon and Pyrex [8].…”
Section: Fabricationmentioning
confidence: 99%
“…An advantage of parylene-C is that it is depositable at room temperature, and it requires no thermal annealing and baking cycles during deposition [2][3][4][5][6][7]. In addition, low stress silicon/Pyrex wafer bonding is also possible by performing the bonding around the stress-free temperature of 270 °C [8], which is sufficiently low to be compatible with CMOS processing.…”
Section: Introductionmentioning
confidence: 99%