Thermal-aware reliability analysis for Platform FPGAs

Mangalagiri, Prasanth; Bae, Sangwoo; Ramakrishnan, K. K.; Xie, Yuan; Narayanan, Vijaykrishnan

doi:10.1109/iccad.2008.4681656

Cited by 23 publications

(13 citation statements)

References 11 publications

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“…Previous studies have shown that hardware resources with increased power densities and thermal stress exhibit higher failure probability [Gielen et al 2008;Black 1969;Mangalagiri et al 2008]. This mainly occurs because a number of important device parameters, such as mobility, threshold voltage, and saturation velocity, depend on temperature values.…”

Section: Motivationmentioning

confidence: 99%

“…Specifically, the Mean-Time-To-Failure (MTTF) due to various intrinsic reliability factors such as electromigration [Srinivasan et al 2004], Time-Dependent Dielectric Breakdown (TDDB), and NBTI [Wang et al 2007] vary exponentially with on-chip temperatures [Gielen et al 2008;Black 1969;Mangalagiri et al 2008;Srinivasan et al 2004;Wang et al 2007]. This problem becomes far more important if we take into consideration the nonuniformity in thermal profile over the chip's area due to variations in the power 169:2 K. Siozios et al density of components.…”

Section: Introductionmentioning

confidence: 99%

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A Framework for Supporting Adaptive Fault-Tolerant Solutions

Siozios

Soudris

Hübner

2014

ACM Trans. Embed. Comput. Syst.

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For decades, computer architects pursued one primary goal: performance. The ever-faster transistors provided by Moore's law were translated into remarkable gains in operation frequency and power consumption. However, the device-level size and architecture complexity impose several new challenges, including a decrease in dependability level due to physical failures. In this article we propose a software-supported methodology based on game theory for adapting the aggressiveness of fault tolerance at runtime. Experimental results prove the efficiency of our solution since it achieves comparable fault masking to relevant solutions, but with significantly lower mitigation cost. More specifically, our framework speeds up the identification of suspicious failure resources on average by 76% as compared to the HotSpot tool. Similarly, the introduced solution leads to average Power×Delay (PDP) savings against an existing TMR approach by 53%. ACM Reference Format:Kostas Siozios, Dimitrios Soudris, and Michael Hübner. 2014. A framework for supporting adaptive fault tolerant solutions.

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Section: Motivationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Framework for Supporting Adaptive Fault-Tolerant Solutions

Siozios

Soudris

Hübner

2014

ACM Trans. Embed. Comput. Syst.

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“…The impact of intrinsic failure mechanisms on the life-time reliability is tightly firmed both on the operating conditions, as well as to design specific attributes [5]. This section proposes a method for rapid classification of FPGA's hardware resources either as suspicious to fail, or not.…”

Section: Motivationmentioning

confidence: 99%

“…Defects at VLSI designs are tightly coupled to the operation conditions. Specifically, the Mean Time To Failure (MTTF) due to various intrinsic reliability factors, such as Electromigration, Time-Dependent Dielectric Breakdown (TDDB) and NBTI, vary exponentially with on-chip temperatures [5].…”

Section: Introductionmentioning

confidence: 99%

On Supporting Adaptive Fault Tolerant at Run-Time with Virtual FPGAs

Siozios

Soudris

Hübner

2013

2013 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum

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For decades computer architects pursued one primary goal: performance. The even-faster transistors provided by Moore's law were translated into remarkable gains in operation frequency and power consumption. However, the device-level size and architecture complexity imposes several new challenges, including a decrease in dependability level due to physical failures. This makes crucial the usage of fault tolerance. Existing solutions are applied statically at design-time ignoring about constraints posed during execution phase, while they also introduce mentionable overheads in terms of delay and power consumption. In this paper we introduce a software-supported methodology based on game theory for adapting the aggressiveness of fault tolerance at run-time. Experimental results prove the efficiency of our methodology since it achieves comparable fault masking to relevant solutions, but with significant lower mitigation cost.

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“…The solder joint fault of FPGA processors could be found in all types of commercial and defence products [1]. Many factors, such as the vibration [2,3] and the temperature circulation [4,5], can lead the solder joint fault. It should be emphasized that this fault would lead the increase of solder joint resistance [6].…”

mentioning

confidence: 99%

Online test method of FPGA solder joint resistance with low power consumption

Wang

et al. 2015

Microelectronics Reliability

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Thermal-aware reliability analysis for Platform FPGAs

Cited by 23 publications

References 11 publications

A Framework for Supporting Adaptive Fault-Tolerant Solutions

A Framework for Supporting Adaptive Fault-Tolerant Solutions

On Supporting Adaptive Fault Tolerant at Run-Time with Virtual FPGAs

Online test method of FPGA solder joint resistance with low power consumption

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